Abstract: A semiconductor device includes a p-type field-effect transistor including first channels made of silicon having a (110) crystallographic orientation. The semiconductor device further includes an n-type field-effect transistor including second channels made of silicon having a (100) crystallographic orientation. The semiconductor device further includes a gate surrounding the first channels and the second channels.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of sections from a top to a bottom thereof, wherein the plurality of sections has a same chemical composition and at least two different strains. For example, in one embodiment, the plurality of sections has a same chemical composition of epitaxially grown silicon (Si) and has alternating strains between a tensile strain and a compressive strain. A method of manufacturing the semiconductor structure is also provided.

Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a bottom field effect transistor (FET); a top FET stacked over the bottom FET, where the top FET has a smaller active area than the bottom FET; a bottom gate formed in contact with the bottom FET; a top gate formed in contact with the top FET; and a bottom contact formed adjacent to the top gate, wherein an inner spacer is formed between the bottom contact and the top gate.

Abstract: An approach provides a semiconductor structure with a first crystalline surface orientation and a first nanosheet stack on the semiconductor substrate with the first crystalline surface orientation. The semiconductor substrate structure includes a second nanosheet stack with a second crystalline surface orientation above the first nanosheet stack, wherein the first nanosheet stack and the second nanosheet stack are separated by a dielectric material.

Abstract: A method of forming a vertical transport fin field effect transistor device is provided. The method includes forming vertical fins on a substrate, depositing a protective liner on the sidewalls of the vertical fins, and removing a portion of the substrate to form a support pillar beneath at least one of the vertical fins. The method further includes etching a cavity in the support pillar of the at least one of the vertical fins, and removing an additional portion of the substrate to form a plinth beneath the support pillar of the vertical fin. The method further includes growing a bottom source/drain layer on the substrate adjacent to the plinth, and forming a diffusion plug in the cavity, wherein the diffusion plug is configured to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar.

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

Abstract: A semiconductor structure includes a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region of the substrate, while the second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers. The semiconductor structure further includes an epitaxially grown encapsulation layer disposed only along sidewalls of the second nanosheet fin.

Abstract: An inner field effect transistor has an inner source, an inner drain, and a group of inner nanosheet channel structures interconnecting the inner source and the inner drain. An outer field effect transistor has an outer source, an outer drain, and a group of outer nanosheet channel structures interconnecting the outer source and the outer drain. An isolation region is located between the inner field effect transistor and the outer field effect transistor. A metal gate stack is located between the inner source and inner drain and between the outer source and the outer drain. The metal gate stack at least partially surrounds the inner and outer nanosheet channel structures. The metal gate stack has a dielectric region adjacent the isolation region.

Abstract: A first and a second nanosheet stack, a first source drain to the first nanosheet stack, a carrier wafer bonded to an upper surface, a bottom source drain contact located on a bottom surface of the first source drain, an epitaxial region between the bottom source drain contact and the first source drain, a second source drain adjacent to the second nanosheet stack and a top source drain contact located on an upper surface of the second source drain, the bottom source drain contact and the top source drain contact on opposite sides. Forming a first and a second nanosheet stack, forming an upper top source drain contact to first source drain adjacent to the first nanosheet stack, bonding a carrier wafer to an upper surface and forming a bottom source drain contact to a lower horizontal surface of a second source drain adjacent to the second nanosheet stack.

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: A first and a second nanosheet stack, a shallow trench isolation region vertically aligned between them, a continuous dielectric layer below the first and second nanosheet stack and above the shallow trench isolation region. The shallow trench isolation region is vertically aligned with a source drain between the first and the second nanosheet stack. A method including forming a first and a second nanosheet stack on a first substrate, the first and the second nanosheet stack each including a lower nanosheet stack vertically aligned above an upper nanosheet stack, the upper nanosheet stack and the lower nanosheet stack each including alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another, flipping the first substrate over, bonding an upper surface of the first substrate to an upper surface of a second substrate which includes a shallow trench isolation region.

Abstract: A semiconductor structure includes a substrate disposed in a horizontal plane, a gate metal on the substrate, a first spacer and a second spacer on the substrate with the gate metal between the first spacer and the second spacer, and a plurality of horizontally stacked nanosheets extending between the first spacer and the second spacer, with the gate metal encapsulating the plurality of horizontally stacked nanosheets between the first spacer and the second spacer.

Abstract: A lower nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material, an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material, one or more dielectric layers between the lower nanosheet stack and the upper nanosheet stack, each separated by an inner spacer. An embodiment where the one or more partial dielectric layers each include an opening. Forming an upper nanosheet stack vertically aligned above an intermediate stack, vertically aligned above a lower nanosheet stack, the upper nanosheet stack, the lower nanosheet stack each including alternating layers of a first sacrificial material and a semiconductor channel material, the intermediate stack including one or more alternating layers of the sacrificial material and a second sacrificial material, recessing the second sacrificial material; and forming second inner spacers where the second sacrificial material was recessed.

Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor structure includes a plurality of nanosheet (NS) channel layers having a plurality of source/drain (S/D) regions on sidewalls thereof; and a continuous contact via being in direct contact with the plurality of S/D regions, wherein the continuous contact via has a substantially same horizontal distance to each of the plurality of NS channel layers. A method of manufacturing the same is also provided.

Abstract: A stacked semiconductor device includes a lower semiconductor device that has a backside and includes a flipped upper semiconductor device that has a backside that is opposed to the lower semiconductor device backside. The flipped upper semiconductor device further includes a backside residual semiconductor on insulator (SOI) layer and a stressed dielectric portion thereupon. The stacked semiconductor device may be formed by stacking and bonding the flipped upper semiconductor device to the lower semiconductor device, removing one or more semiconductor on insulator (SOI) layers from the backside of the flipped upper semiconductor device while retaining an exposed backside residual SOI layer of the flipped upper semiconductor device, forming a stressed dielectric layer upon the exposed backside residual SOI layer, and patterning the stressed dielectric layer.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of sections from a top to a bottom thereof, wherein the plurality of sections has a same chemical composition and at least two different strains. For example, in one embodiment, the plurality of sections has a same chemical composition of epitaxially grown silicon (Si) and has alternating strains between a tensile strain and a compressive strain. A method of manufacturing the semiconductor structure is also provided.

Abstract: A gate-all-around device is provided. The gate-all-around device includes a source/drain on a substrate, an isolation liner wrapped around the source/drain, where the isolation liner separates the source/drain from the substrate, and a one or more nanosheet channel sections electrically connected to the source/drain.

Abstract: Semiconductor devices and methods of forming the same include forming a buried power rail in a substrate, having a first dielectric liner of a first thickness separating the buried power rail from the substrate. An isolation structure is formed over the buried power rail, having a second dielectric liner of a second thickness, greater than the first thickness, separating the isolation structure from the substrate. A first transistor device is formed on the substrate. The first transistor device has a first width. A second transistor device is formed above the first transistor device, and has a second width smaller than the first width. A conductive contact is formed to the buried power rail.