Patents by Inventor Shogo Mochizuki

Shogo Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10249714
    Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 2, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Dechao Guo, Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh
  • Patent number: 10249502
    Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 10243043
    Abstract: A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner spacer liner and an air gap are present. Collectively, each inner spacer liner and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • Patent number: 10242919
    Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki, Chun W. Yeung
  • Patent number: 10236360
    Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10229975
    Abstract: A method includes forming an oxide layer on a silicon-germanium (SiGe) fin formed on a substrate. The first oxide layer comprises a mixture of a germanium oxide compound (GeOx) and a silicon oxide compound (SiOx). The first oxide layer is modified to create a Si-rich outer surface of the SiGe fin. A silicon nitride layer is deposited on the modified first oxide layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki, Koji Watanabe
  • Patent number: 10217863
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, including forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Junli Wang
  • Publication number: 20190035923
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Publication number: 20190019889
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, including forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 17, 2019
    Inventors: Shogo Mochizuki, Junli Wang
  • Patent number: 10177169
    Abstract: A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Ali Khakifirooz, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10170620
    Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10164103
    Abstract: A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shogo Mochizuki, Jie Yang
  • Publication number: 20180358465
    Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
    Type: Application
    Filed: November 9, 2017
    Publication date: December 13, 2018
    Inventors: Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh
  • Publication number: 20180358269
    Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.
    Type: Application
    Filed: April 26, 2018
    Publication date: December 13, 2018
    Inventors: Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki, Chun W. Yeung
  • Publication number: 20180358460
    Abstract: A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: Kangguo Cheng, Shogo Mochizuki, Jie Yang
  • Publication number: 20180358268
    Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.
    Type: Application
    Filed: April 26, 2018
    Publication date: December 13, 2018
    Inventors: Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki, Chun W. Yeung
  • Publication number: 20180358435
    Abstract: A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner dielectric liner and an air gap are present. Collectively, each inner spacer and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.
    Type: Application
    Filed: November 14, 2017
    Publication date: December 13, 2018
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • Patent number: 10141426
    Abstract: According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The method also includes performing an isotropic etching process to remove portions of the semiconductor substrate in the first cavity and form a first undercut region below the liner layer, growing a first epitaxial semiconductor material in the first undercut region and the first cavity, and performing a first annealing process to drive dopants from the first epitaxial semiconductor material into the first fin to form a first source/drain layer under the first fin and in portions of the semiconductor substrate.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACAHINES CORPORATION
    Inventors: Brent A. Anderson, Huiming Bu, Fee Li Lie, Shogo Mochizuki, Junli Wang
  • Publication number: 20180337277
    Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.
    Type: Application
    Filed: February 27, 2018
    Publication date: November 22, 2018
    Inventors: Ruqiang Bao, ChoongHyun Lee, Shogo Mochizuki, Hemanth Jagannathan
  • Patent number: 10134763
    Abstract: The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the gate structures. A replacement metal gate process used in the fabrication of such devices includes formation of the inner spacers following partial removal of dummy gate material. The remaining dummy gate material is then removed and replaced with gate dielectric and metal gate material.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek