Abstract: A device comprises a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between the first and second interconnect structures. The stacked complementary transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type. The first contact connects a first source/drain element of the first transistor to the first interconnect structure. The second contact connects a first source/drain element of the second transistor to the second interconnect structure. The first and second contacts are disposed in alignment with each other.

Abstract: A semiconductor structure includes a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region of the substrate, while the second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers. The semiconductor structure further includes an epitaxially grown encapsulation layer disposed only along sidewalls of the second nanosheet fin.

Abstract: A semiconductor structure includes a source/drain region having a top surface comprising a planar portion and at least one recessed portion. A metal contact is disposed on the source/drain region.

Abstract: Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a stacked field effect transistor (stacked-FET). The stacked-FET includes a top FET having multiple top channels having multiple nano-sheets in contact with corresponding nano-sheets in a corresponding top channels for an active gate. The stacked-FET includes multiple bottom channels having a dielectric material. The semiconductor structure also includes an active gate. The active gate includes the corresponding top channels and corresponding bottom channels having the dielectric material.

Abstract: A GAA (gate-all-around) semiconductor device includes a first source/drain region comprising an epitaxially grown first buffer layer disposed in contact with first device channel inner spacers and a device substrate, and an epitaxially grown first source/drain disposed adjacent to the first buffer layer. The device also includes a second source/drain region comprising an epitaxially grown second buffer layer disposed in contact with second device channel inner spacers and the device substrate, and an epitaxially grown second source/drain disposed adjacent to the second buffer layer. The first source/drain region and the second source/drain region are disposed on opposing sides of a device gate structure. The device gate structure comprising semiconductor nanosheet channels disposed between the first source/drain region and the second source/drain region.

Abstract: A semiconductor channel material structure is provided that has an improved, i.e., increased, effective channel area. The semiconductor channel material structure includes a plurality of semiconductor channel material nanosheets stacked one atop the other. The increased channel area is afforded by providing at least one through-stack semiconductor channel material that extends through at least one of the semiconductor channel material nanosheets.

Abstract: A vertical field-effect transistor device includes a substrate comprising a semiconductor material, and a set of fins formed from the semiconductor material and extending vertically with respect to the substrate. The vertical field-effect transistor device further includes gate structures disposed on the substrate and on a portion of sidewalls of the set of fins, spacers disposed on the gate structures and on a remaining portion of the sidewalls of the set of fins, source/drain regions disposed over top portions of the set of fins, and a metal liner disposed adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions. A portion of the source/drain regions is configured to have a lateral width less than a width between adjacent gate structures on the respective fin.

Abstract: Embodiments of the invention are directed to a semiconductor-based structure that includes a stack having spaced-apart non-sacrificial nanosheets. A source or drain (S/D) trench is adjacent to the stack, wherein the S/D trench includes a bottom surface and sidewalls. A S/D template layer includes a continuous layer of a first type of semiconductor material, wherein the S/D template layer is within a portion of the S/D trench, on the bottom surface of the S/D trench, and on the sidewalls of the S/D trench. A doped S/D region is on the S/D template layer and within the S/D trench. In some aspects of the invention, the doped S/D region includes a second type of semiconductor material configured to induce strain in the spaced-apart non-sacrificial nanosheets.

Abstract: An approach provides a semiconductor structure with a first crystalline surface orientation and a first nanosheet stack on the semiconductor substrate with the first crystalline surface orientation. The semiconductor substrate structure includes a second nanosheet stack with a second crystalline surface orientation above the first nanosheet stack, wherein the first nanosheet stack and the second nanosheet stack are separated by a dielectric material.

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.

Abstract: A dielectric layer is on top of a first semiconductor stack. The first semiconductor stack is compressively strained. A second semiconductor stack is on top of the dielectric layer. The second semiconductor stack is tensely strained.

Abstract: A semiconductor structure includes a substrate comprising a semiconductor material, and a fin on the substrate. The fin includes a first portion formed from the semiconductor material and a second portion including a channel region. The first portion has a first thickness and the second portion has a second thickness greater than the first thickness. A spacer is disposed on sides of the first portion of the fin.

Abstract: VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.

Abstract: A semiconductor structure includes a p-type field-effect transistor region and an n-type field-effect transistor region. The p-type field-effect transistor region includes a strained channel of a composite of silicon germanium and silicon. The n-type field-effect transistor region includes a silicon channel.

Abstract: A semiconductor device including a fin structure formed on a first semiconductor region, and a first semiconductor structure controlling the first semiconductor region, the first semiconductor structure formed on a substrate and spaced apart from the first semiconductor region including the fin structure.

Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

Abstract: A semiconductor device includes a source/drain (S/D) region, a fin structure formed on the S/D region, and a gate structure formed on the fin structure so that a space is formed between the S/D region and the gate structure.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.