Abstract: Devices and methods are provided to fabricate nanosheet field-effect transistor devices having dummy nanosheet channel layers disposed above active nanosheet channel layers to protect the active nanosheet channel layers from oxidation during work function metal patterning processes that are implemented as part of a multi-threshold voltage process module. The dummy nanosheet channel layers have a reduced thickness so that the dummy nanosheet layers do not function as active channel layers of the nanosheet field-effect transistor devices. The dummy nanosheet channel layers serve as oxygen infusion blocking layers to protect the active nanosheet channel layers from being infused with oxygen and oxidized by a directional plasma etch process performed during a work function metal patterning process.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein each fin of the plurality of fins includes silicon germanium. A layer of silicon germanium oxide is deposited on the plurality of fins, and a first thermal annealing process is performed to convert outer regions of the plurality of fins into a plurality of silicon portions. Each silicon portion of the plurality of silicon portions is formed on a silicon germanium core portion. The method further includes forming a plurality of source/drain regions on the substrate, and depositing a layer of germanium oxide on the plurality of source/drain regions. A second thermal annealing process is performed to convert outer regions of the plurality of source/drain regions into a plurality of germanium condensed portions.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.

Abstract: A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.

Abstract: A method for forming the semiconductor device that includes forming an etch mask covering a drain side of the gate structure and the silicon containing fin structure; etching a source side of the silicon containing fin structure adjacent to the channel region; and forming a germanium containing semiconductor material on an etched sidewall of the silicon containing fin structure adjacent to the channel region. Germanium from the germanium containing semiconductor material is diffused into the channel region to provide a graded silicon germanium region in the channel region having germanium present at a highest concentration in the channel region at the source end of the channel region and a germanium deficient concentration at the drain end of the channel region.

Abstract: A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins.

Abstract: Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same.

Abstract: Methods of fabrication and semiconductor structures includes vertical transport field effect transistors (VTFETs) including a top source/drain extension formed with a sacrificial doped layer. The sacrificial doped layer provides the doping source to form the extension and protects the top of the fin during fabrication so as to prevent thinning, among other advantages.

Abstract: Embodiments of the invention are directed to a method that includes forming a nanosheet stack over a substrate. The nanosheet stack includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region. The first end region, the second end region, and the central region each includes a first type of semiconductor material, wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant. The central region is converted to a second type of semiconductor material, wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.

Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

Abstract: The disclosure provides a frozen dessert composition comprising (A) about 6 to 15% by weight of palatinose based on the total weight of the composition, and (B) about 10 to 30% by weight of a dextrin or a combination of a dextrin and a soluble dietary fiber based on the total weight of the composition. The disclosure also provides a method of manufacturing a frozen dessert composition comprising mixing the following components with water; (A) about 6 to 15% by weight of palatinose based on the total weight of the composition, and (B) about 10 to 30% by weight of a dextrin or a combination of a dextrin and a soluble dietary fiber based on the total weight of the composition.

Abstract: Device structures and methods are provided for fabricating vertical field-effect transistor devices with non-uniform thickness bottom spacers to achieve increased device performance. For example, a semiconductor substrate surface is etched to form semiconductor fins having bottom portions with concave sidewall surfaces that undercut upper portions of the fins. A doped epitaxial source/drain layer is formed on the concave sidewall surfaces, wherein portions of the doped epitaxial source/drain layer disposed between the fins have a raised curved surface. A bottom spacer layer is formed on the doped epitaxial source/drain layer, wherein portions of the bottom spacer layer disposed between the fins have a curved-shaped profile with a non-uniform thickness.

Abstract: A nanosheet transistor device having reduced access resistance is fabricated by recessing channel nanosheets and replacing the channel material with epitaxially grown doped extension regions. Sacrificial semiconductor layers between the channel nanosheets are selectively removed without damaging source/drain regions epitaxially grown on the extension regions. The sacrificial semiconductor layers are replaced by gate dielectric and gate metal layers.

Abstract: Embodiments of the invention are directed to a method that includes forming a nanosheet stack over a substrate. The nanosheet stack includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region. The first end region, the second end region, and the central region each includes a first type of semiconductor material, wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant. The central region is converted to a second type of semiconductor material, wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.

Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.

Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate over a fin, which has a lower semiconductor layer, an insulating intermediate layer, and an upper semiconductor layer, to establish a channel region and source/drain regions. Source/drain extensions are grown on the lower semiconductor layer. Source/drain extensions are grown on the upper semiconductor layer. The dummy gate is replaced with a gate stack.

Abstract: A technique relates to a semiconductor device. Fins are formed of varying concentrations of germanium. Gate material is formed on the fins. Source or drain (S/D) regions are adjacent to the fins, and transistor devices include the fins.

Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.

Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

Abstract: A method of forming a semiconductor device that includes forming a vertically orientated channel in a semiconductor fin structure that is present on a supporting substrate; and depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure that is opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate. The method further includes recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure.