Patents by Inventor Shogo Mochizuki

Shogo Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180240875
    Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 23, 2018
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Chun-chen Yeh
  • Patent number: 10056503
    Abstract: MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10056484
    Abstract: Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Shogo Mochizuki
  • Publication number: 20180219026
    Abstract: A semiconductor structure is provided that includes a plurality of high mobility semiconductor material (i.e., silicon germanium alloy of III-V compound semiconductors) fins located above and spaced apart from a bulk semiconductor substrate portion, wherein each of the high mobility semiconductor material fins has a lower faceted surface that is confined within a dielectric isolation structure.
    Type: Application
    Filed: March 29, 2018
    Publication date: August 2, 2018
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Publication number: 20180211885
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOX) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOX) and removal of the GeOX results in formation of a pure silicon dioxide (SiO2) layer.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 26, 2018
    Inventors: Ruqiang Bao, Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki
  • Patent number: 10032912
    Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 24, 2018
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pierre Morin, Kangguo Cheng, Jody Fronheiser, Xiuyu Cai, Juntao Li, Shogo Mochizuki, Ruilong Xie, Hong He, Nicolas Loubet
  • Patent number: 10020384
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 10, 2018
    Inventors: Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10020303
    Abstract: Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: July 10, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Hong He, Shogo Mochizuki, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Publication number: 20180190794
    Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.
    Type: Application
    Filed: February 15, 2018
    Publication date: July 5, 2018
    Inventors: OLEG GLUSCHENKOV, SANJAY C. MEHTA, SHOGO MOCHIZUKI, ALEXANDER REZNICEK
  • Patent number: 10008417
    Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki, Chun W. Yeung
  • Publication number: 20180175197
    Abstract: Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.
    Type: Application
    Filed: January 30, 2018
    Publication date: June 21, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Alexander REZNICEK, Shogo MOCHIZUKI, Veeraraghavan S. BASKER, Nicolas L. BREIL, Oleg GLUSCHENKOV
  • Patent number: 9997407
    Abstract: Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that contains a void within a contact opening. The void is then opened to provide a divot in the first contact metal. After forming a dielectric spacer atop a portion of first contact metal, a second contact metal is then formed that lacks any void. The second contact metal fills the entirety of the divot within the first contact metal. In another embodiment, two diffusion barrier structures are provided within a contact opening, followed by the formation of a contact metal structure that lacks any void.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 9991255
    Abstract: Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 5, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Hong He, Shogo Mochizuki, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9991382
    Abstract: A semiconductor structure is provided that includes a vertical transport field effect transistor located on sidewall surfaces of a semiconductor fin. The semiconductor structure further includes an abrupt junction that is located between a bottom source/drain extension region and a sidewall surface of a lower portion of the semiconductor fin. The bottom source/drain extension region is present in a gap that is located adjacent the lower portion of the semiconductor fin and atop a mesa portion of a base semiconductor substrate.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Alexander Reznicek
  • Patent number: 9991258
    Abstract: Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: June 5, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Hong He, Shogo Mochizuki, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9985114
    Abstract: A method of forming a semiconductor device that includes providing a plurality of fin structures, wherein a surface of the fin structures has a first orientation for a diamond shaped epitaxial growth deposition surface. A first epitaxial semiconductor material having a diamond geometry is grown on the diamond shaped epitaxial growth surface. A blocking material is formed protecting a lower portion of the first epitaxial semiconductor material. An upper portion of the first epitaxial semiconductor material is removed to expose a second orientation surface of the first epitaxial semiconductor material for merged epitaxial semiconductor growth. A second epitaxial semiconductor material is epitaxially formed on the first epitaxial semiconductor material. The second epitaxial semiconductor material has a substantially planar upper surface and extends into direct contact with at least two adjacent fin structures.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Publication number: 20180145092
    Abstract: The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the gate structures. A replacement metal gate process used in the fabrication of such devices includes formation of the inner spacers following partial removal of dummy gate material. The remaining dummy gate material is then removed and replaced with gate dielectric and metal gate material.
    Type: Application
    Filed: December 31, 2017
    Publication date: May 24, 2018
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Publication number: 20180138296
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 17, 2018
    Inventors: Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 9972682
    Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Chun-chen Yeh
  • Patent number: 9966253
    Abstract: A nanotip apparatus which includes nanotips arranged in a pattern on a semiconductor base. Each of the nanotips have a pointed tip portion and a base portion in contact with the semiconductor base. Further, each of the nanotips include a gradient of silicon germanium (SiGe) with the highest concentration of germanium being at the pointed tip portion and the lowest concentration of germanium being at the base in contact with the semiconductor base. Also disclosed is a method in which the nanotips may be formed.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 8, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li, Shogo Mochizuki