Patents by Inventor Shoji Akiyama
Shoji Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9405184Abstract: Here are disclosed a pellicle for EUV and an assembly made up of this pellicle and a mask, which brings about a projection of low contrast (intensity) shadows of a mesh structure on the mask, thus minimizing the adverse effect of the shadow on the lithographic printing; also a method for assembling such assembly is disclosed wherein the pellicle is rotated relative to the mask to minimize the shadow contrast, in terms of a contrast ratio, of the mesh structure; the angle of the rotation is 30 degrees or smaller, and the resultant contrast ratio should be 25% or lower.Type: GrantFiled: January 16, 2015Date of Patent: August 2, 2016Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Motoyuki Yamada, Shoji Akiyama
-
Patent number: 9312166Abstract: This invention provides a method for manufacturing composite wafers in which at least two composite wafers can be obtained from one donor wafer, and in which the chamfering step can be omitted. Provided is a method for manufacturing composite wafers comprising: bonding surfaces of at least two handle wafers and a surface of a donor wafer which has a diameter greater than or equal to a sum of diameters of the at least two handle wafers and which has a hydrogen ion implantation layer formed inside thereof by implanting hydrogen ions from the surface of the donor wafer, to obtain a bonded wafer; heating the bonded wafer at 200° C. to 400° C.; and detaching a film from the donor wafer along the hydrogen ion implantation layer of the heated bonded wafer, to obtain the composite wafers having the film transferred onto the at least two handle wafers.Type: GrantFiled: September 14, 2012Date of Patent: April 12, 2016Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Kazutoshi Nagata
-
Publication number: 20160071761Abstract: A hybrid substrate has an SOI structure having a good silicon active layer, without defects such as partial separation of the silicon active layer is obtained without trimming the outer periphery of the substrate. An SOI substrate is obtained by sequentially laminating a first silicon oxide film and a silicon active layer in this order on a silicon substrate. A terrace portion that does not have the silicon active layer is formed in the outer peripheral portion of the silicon substrate surface. A second silicon oxide film is formed on the silicon active layer surface of the SOI substrate The bonding surfaces of the SOI substrate and a supporting substrate that has a thermal expansion coefficient different from that of the SOI substrate is subjected to an activation treatment. The SOI substrate and the supporting substrate are bonded with the second silicon oxide film being interposed therebetween.Type: ApplicationFiled: April 21, 2014Publication date: March 10, 2016Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Yuji Tobisaka, Shoji Akiyama, Yoshihiro Kubota, Makoto Kawai, Kazutoshi Nagata
-
Publication number: 20160045916Abstract: A microchip is provided, which includes a substrate including a fluid channel structure. The fluid channel structure includes a first fluid introduction channel and a second fluid introduction channel configured to meet so as to allow merging of a first fluid introduced from the first fluid introduction channel and a second fluid introduced from the second fluid introduction channel. A tapered portion is configured to be positioned after merging the first fluid and the second fluid so as to suppress a spiral flow field generated after the merging.Type: ApplicationFiled: October 9, 2015Publication date: February 18, 2016Inventors: Tatsumi ITO, Shoji AKIYAMA, Masaya KAKUTA, Takeshi YAMASAKI
-
Patent number: 9214379Abstract: A bonded SOS substrate having a semiconductor film on or above a surface of a sapphire substrate is obtained by a method with the steps of implanting ions from a surface of a semiconductor substrate to form an ion-implanted layer; activating at least a surface from which the ions have been implanted; bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at a temperature of 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to form a bonded body; and irradiating visible light from a sapphire substrate side or a semiconductor substrate side to the ion-implanted layer of the semiconductor substrate for embrittling an interface of the ion-implanted layer, while keeping the bonded body at a temperature higher than the temperature at which the surfaces of the semiconductor substrate and the sapphire substrate were bonded.Type: GrantFiled: July 8, 2013Date of Patent: December 15, 2015Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Shoji Akiyama, Atsuo Ito, Yuji Tobisaka, Makoto Kawai
-
Patent number: 9214380Abstract: Method of making a bonded SOS substrate with a semiconductor film on or above a sapphire substrate by implanting ions from a surface of the semiconductor substrate to form an ion-implanted layer; activating at least a surface of one of the sapphire substrate and the semiconductor substrate from which the ions have been implanted; bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at a temperature of from 50° C. to 350° C.; heating the bonded substrates at a maximum temperature of from 200° C. to 350° C.; and irradiating visible light from a sapphire substrate side or a semiconductor substrate side to the ion-implanted layer of the semiconductor substrate to make the interface of the ion-implanted layer brittle at a temperature of the bonded body higher than the temperature at which the surfaces were bonded, to transfer the semiconductor film to the sapphire substrate.Type: GrantFiled: July 19, 2013Date of Patent: December 15, 2015Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Shoji Akiyama, Atsuo Ito, Yuji Tobisaka, Makoto Kawai
-
Patent number: 9195130Abstract: A pellicle for EUV including a silicon film and a mesh work structure supporting the silicon film, and this pellicle is improved in that the grid frames of the mesh work structure are tapered in such a manner that the width of each grid frame lessens as the distance from the silicon film is increased.Type: GrantFiled: September 3, 2013Date of Patent: November 24, 2015Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Motoyuki Yamada, Shoji Akiyama
-
Patent number: 9176042Abstract: A microchip is provided which includes a first introduction channel, second introduction channels arranged to sandwich the first introduction channel and merged with the first introduction channel from both sides, and a merge channel connected to the first introduction channel and the second introduction channels, where fluids fed from the first and the second introduction channels are merged and flow, wherein the merge channel has a tapered portion formed so that a channel width in a sandwiching direction along which the first introduction channel is sandwiched by the second introduction channels gradually increases along a fluid feeding direction.Type: GrantFiled: February 18, 2011Date of Patent: November 3, 2015Assignee: SONY CORPORATIONInventors: Tatsumi Ito, Shoji Akiyama, Masaya Kakuta, Takeshi Yamasaki
-
Publication number: 20150205193Abstract: Here are disclosed a pellicle for EUV and an assembly made up of this pellicle and a mask, which brings about a projection of low contrast (intensity) shadows of a mesh structure on the mask, thus minimizing the adverse effect of the shadow on the lithographic printing; also a method for assembling such assembly is disclosed wherein the pellicle is rotated relative to the mask to minimize the shadow contrast, in terms of a contrast ratio, of the mesh structure; the angle of the rotation is 30 degrees or smaller, and the resultant contrast ratio should be 25% or lower.Type: ApplicationFiled: January 16, 2015Publication date: July 23, 2015Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Motoyuki Yamada, Shoji Akiyama
-
Publication number: 20150179506Abstract: A method for producing SOS substrates which can be incorporated into a semiconductor production line, and is capable of producing SOS substrates which have few defects and no variation in defects, and in a highly reproducible manner, or in other words, a method for producing SOS substrates by: forming an ion-injection region (3) by injecting ions from the surface of a silicon substrate (1); adhering the ion-injection surface of the silicon substrate (1) and the surface of a sapphire substrate (4) to one another directly or with an insulating film (2) interposed therebetween; and then obtaining an SOS substrate (8) having a silicon layer (6) on the sapphire substrate (4), by detaching the silicon substrate in the ion-injection region (3). This method is characterized in that the orientation of the sapphire substrate (4) is a C-plane having an off-angle of 1 degree or less.Type: ApplicationFiled: July 18, 2013Publication date: June 25, 2015Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Shigeru Konishi, Yoshihiro Kubota, Makoto Kawai, Shoji Akiyama, Kazutoshi Nagata
-
Patent number: 9064929Abstract: There is disclosed a method for manufacturing an SOI wafer comprising: a step of implanting at least one of a hydrogen ion and a rare gas ion into a donor wafer to form an ion implanted layer; a step of bonding an ion implanted surface of the donor wafer to a handle wafer; a step of delaminating the donor wafer at the ion implanted layer to reduce a film thickness of the donor wafer, thereby providing an SOI layer; and a step of etching the SOI layer to reduce a thickness of the SOI layer, wherein the etching step includes: a stage of performing rough etching as wet etching; a stage of measuring a film thickness distribution of the SOI layer after the rough etching; and a stage of performing precise etching as dry etching based on the measured film thickness distribution of the SOI layer. There can be provided A method for manufacturing an SOI wafer having high film thickness uniformity of an SOI layer with excellent productivity.Type: GrantFiled: May 20, 2008Date of Patent: June 23, 2015Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
-
Publication number: 20150108502Abstract: The present invention relates to a heat dissipation substrate, which is a composite substrate composed of two layers, and which is characterized in that a surface layer (first layer) (1) is configured of single crystal silicon and a handle substrate (second layer) (2) is configured of a material that has a higher thermal conductivity than the first layer. A heat dissipation substrate of the present invention has high heat dissipation properties.Type: ApplicationFiled: May 7, 2013Publication date: April 23, 2015Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Yoshihiro Kubota, Makoto Kawai
-
Patent number: 8975159Abstract: A method for manufacturing a bonded wafer having a semiconductor film on a handle substrate involving the steps of: implanting ions into a semiconductor substrate to form an ion-implanted layer; subjecting the surface of at least one of the semiconductor substrate and the handle substrate to a surface activation treatment; bonding the surface of the semiconductor substrate to the surface of the handle substrate at a temperature from 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to obtain a bonded body; and transferring a semiconductor film to the handle substrate by subjecting the bonded body to a temperature 30° C. to 100° C. higher than the bonding temperature, and irradiating the bonded body with visible light from a handle or semiconductor substrate side toward the ion-implanted layer of the semiconductor substrate to embrittle the interface of the ion-implanted layer.Type: GrantFiled: May 6, 2010Date of Patent: March 10, 2015Assignee: Shin-Etsu Chemical Co., Ltd.Inventor: Shoji Akiyama
-
Patent number: 8937721Abstract: A detection device is disclosed which includes: a detection plate in which a silicon layer and a silicon oxide layer are arranged in this order on a silica glass substrate; and optical prism which is optically adhered to a surface of the silica glass substrate of the detection plate, where the surface is not provided with the silicon layer and the silicon oxide layer; a light-irradiation unit configured to irradiate light to the detection plate through the optical prism and arranged so that light is incident on the optical prism with a fixed incident angle; and a light-detection unit configured to detect intensity of reflected light reflected from the detection plate, wherein the detection device detects a change in dielectric constant by detecting a change in property of the reflected light.Type: GrantFiled: November 15, 2011Date of Patent: January 20, 2015Assignees: National Institute of Advanced Industrial Science and Technology, Shin-Etsu Chemical Co., Ltd.Inventors: Makoto Fujimaki, Shoji Akiyama, Kazutoshi Nagata
-
Publication number: 20140322546Abstract: A thermally oxidized heterogeneous composite substrate provided with a single crystal silicon film on a handle substrate, said heterogeneous composite substrate being obtained by, prior to a thermal oxidization treatment at a temperature exceeding 850° C., conducting an intermediate heat: treatment at 650-850° C. and then conducting the thermal oxidization treatment at a temperature exceeding 850° C. According to the present invention, a thermally oxidized heterogeneous composite substrate with a reduced number of defects after thermal oxidization can be obtained.Type: ApplicationFiled: January 11, 2013Publication date: October 30, 2014Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Shoji Akiyama, Yuji Tobisaka, Kazutoshi Nagata
-
Publication number: 20140308800Abstract: This invention provides a method for manufacturing composite wafers in which at least two composite wafers can be obtained from one donor wafer, and in which the chamfering step can be omitted. Provided is a method for manufacturing composite wafers comprising: bonding surfaces of at least two handle wafers and a surface of a donor wafer which has a diameter greater than or equal to a sum of diameters of the at least two handle wafers and which has a hydrogen ion implantation layer formed inside thereof by implanting hydrogen ions from the surface of the donor wafer, to obtain a bonded wafer; heating the bonded wafer at 200° C. to 400° C.; and detaching a film from the donor wafer along the hydrogen ion implantation layer of the heated bonded wafer, to obtain the composite wafers having the film transferred onto the at least two handle wafers.Type: ApplicationFiled: September 14, 2012Publication date: October 16, 2014Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Shoji Akiyama, Kazutoshi Nagata
-
Publication number: 20140235032Abstract: The method for producing a transparent SOI wafer is provided and includes treating a bonded wafer at a first temperature of 150 to 300° C. as a first heat treatment; cutting off an unbonded portion of the bonded wafer by irradiating a visible light laser from a silicon wafer side of the heated bonded wafer to a boundary between the bonded surface and an unbonded circumferential surface, while keeping an angle of 60 to 90° between the incident light and a radial direction of the silicon wafer; subjecting the silicon wafer of the bonded wafer having the unbonded portion cut off to grinding, polishing, or etching to form a silicon film; and heat-treating the bonded wafer having the silicon film formed at a second temperature of 300 to 500° C. as a second heat treatment which is higher than the first temperature.Type: ApplicationFiled: October 11, 2012Publication date: August 21, 2014Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Kazutoshi Nagata
-
Patent number: 8772132Abstract: A method of manufacturing a laminated wafer is provided by forming a silicon film layer on a surface of an insulating substrate comprising the steps in the following order of: applying a surface activation treatment to both a surface of a silicon wafer or a silicon wafer to which an oxide film is layered and a surface of the insulating substrate followed by laminating in an atmosphere of temperature exceeding 50° C. and lower than 300° C., applying a heat treatment to a laminated wafer at a temperature of 200° C. to 350° C., and thinning the silicon wafer by a combination of grinding, etching and polishing to form a silicon film layer.Type: GrantFiled: June 28, 2013Date of Patent: July 8, 2014Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Yoshihiro Nojima
-
Patent number: 8765576Abstract: A method of manufacturing a laminated substrate is provided. The method includes: forming an oxide film on at least a surface of a first substrate having a hardness of equal to or more than 150 GPa in Young's modulus, and then smoothing the oxide film; implanting hydrogen ions or rare gas ions, or mixed gas ions thereof from a surface of a second substrate to form an ion-implanted layer inside the substrate, laminating the first substrate and the second substrate through at least the oxide film, and then detaching the second substrate in the ion-implanted layer to form a laminated substrate; heat-treating the laminated substrate and diffusing outwardly the oxide film.Type: GrantFiled: August 28, 2009Date of Patent: July 1, 2014Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Atsuo Ito, Yoshihiro Kubota, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
-
Patent number: D757580Type: GrantFiled: March 7, 2014Date of Patent: May 31, 2016Assignee: Sony CorporationInventors: Yuji Akiyama, Shoji Akiyama, Gakuji Hashimoto, Hiroto Kasai, Masaya Kakuta, Takeshi Yamasaki, Tatsumi Ito, Masataka Shinoda