Patents by Inventor Shosuke Fujii

Shosuke Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240057313
    Abstract: A semiconductor device includes a semiconductor substrate, a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film, a second layer formed above the first layer and including a channel including an oxide semiconductor and a second insulating film, and a third layer formed above the second layer, and including an electrode formed on the channel and a third insulating film having a film density less than at least one of a film density of the first insulating film or a film density of the second insulating film.
    Type: Application
    Filed: March 7, 2023
    Publication date: February 15, 2024
    Applicant: Kioxia Corporation
    Inventors: Taro SHIOKAWA, Takeru MAEDA, Kotaro NODA, Shosuke FUJII
  • Publication number: 20230422482
    Abstract: A semiconductor device according to an embodiment includes: a first electrode; a second electrode; a gate electrode between the first electrode and the second electrode; a first insulating layer; a second insulating layer; a gate insulating layer surrounding the gate electrode; an oxide semiconductor layer surrounding the gate insulating layer, the oxide semiconductor layer including a first region between the gate insulating layer and the first electrode, a second region between the gate insulating layer and the second electrode, a third region between the gate insulating layer and the first insulating layer, and a fourth region between the gate insulating layer and the second insulating layer. A first thickness of the first region and a second thickness of the second region are equal to or less than at least one of a third thickness of the third region or a fourth thickness of the fourth region.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Shosuke FUJII, Kotaro NODA
  • Publication number: 20230422484
    Abstract: According to one embodiment, a semiconductor device includes a first insulating layer, a gate electrode layer provided on the first insulating layer, a second insulating layer provided on the gate electrode layer, an oxide semiconductor layer provided along the second insulating layer, the gate electrode layer and the first insulating layer, a gate insulating layer provided along the second insulating layer, the gate electrode layer and the first insulating layer, and surrounding a side surface of the oxide semiconductor layer, and a first hydrogen barrier film surrounding the oxide semiconductor layer and the gate insulating layer.
    Type: Application
    Filed: November 10, 2022
    Publication date: December 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Tatsuki KIKUCHI, Keiko SAKUMA, Shosuke FUJII
  • Publication number: 20230402395
    Abstract: A semiconductor device includes: a semiconductor substrate including a first area and a second area; a plurality of memory cells provided in the first area; a mark provided in the second area and having a first side surface and a second side surface that intersects with the first side surface; and a plurality of patterns provided in the second area and provided on the first side surface and the second side surface.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 14, 2023
    Applicant: Kioxia Corporation
    Inventors: Kotaro NODA, Kyoko NODA, Shosuke FUJII, Yusuke ARAYASHIKI, Hiroyuki ODE
  • Publication number: 20230402322
    Abstract: A semiconductor device according to an embodiment includes a first conductor, a first oxide semiconductor, a first insulator, a second conductor, a third conductor, and a fourth conductor. The first oxide semiconductor contacts, at one end, the first conductor, and extends in a first direction intersecting a surface of the first conductor. The first insulator surrounds a side surface of the first oxide semiconductor. The second conductor and the first oxide semiconductor interpose the first insulator therebetween. The third conductor contacts another end of the first oxide semiconductor. The fourth conductor extends in a second direction intersecting the first direction, and contacts a second conductor on a side opposite to the first insulator. The second conductor is of a material with a higher work function than a material of the fourth conductor.
    Type: Application
    Filed: March 13, 2023
    Publication date: December 14, 2023
    Applicant: Kioxia Corporation
    Inventors: Shoichi Kabuyanagi, Tsuyoshi Sugisaki, Shosuke Fujii
  • Patent number: 11665908
    Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 30, 2023
    Assignee: Kioxia Corporation
    Inventors: Haruka Sakuma, Hidenori Miyagawa, Shosuke Fujii, Kiwamu Sakuma, Fumitaka Arai, Kunifumi Suzuki
  • Patent number: 10916654
    Abstract: The semiconductor memory device of the embodiment includes a stacked body including interlayer insulating layers and gate electrode layers alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a first insulating layer provided between the semiconductor layer and the gate electrode layers; conductive layers provided between the first insulating layer and the gate electrode layers; and second insulating layers provided between the conductive layers and the gate electrode layers and the second insulating layers containing ferroelectrics. Two of the conductive layers adjacent to each other in the first direction are separated by one of the interlayer insulating layers interposed between the two of the conductive layers, and a first thickness of one of the gate electrode layers in the first direction is smaller than a second thickness of one of the conductive layers in the first direction.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Shosuke Fujii
  • Patent number: 10833103
    Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Haruka Sakuma, Hidenori Miyagawa, Shosuke Fujii, Kiwamu Sakuma, Fumitaka Arai
  • Publication number: 20200303558
    Abstract: The semiconductor memory device of the embodiment includes a stacked body including interlayer insulating layers and gate electrode layers alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a first insulating layer provided between the semiconductor layer and the gate electrode layers; conductive layers provided between the first insulating layer and the gate electrode layers; and second insulating layers provided between the conductive layers and the gate electrode layers and the second insulating layers containing ferroelectrics. Two of the conductive layers adjacent to each other in the first direction are separated by one of the interlayer insulating layers interposed between the two of the conductive layers, and a first thickness of one of the gate electrode layers in the first direction is smaller than a second thickness of one of the conductive layers in the first direction.
    Type: Application
    Filed: August 23, 2019
    Publication date: September 24, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Shosuke FUJII
  • Publication number: 20200303418
    Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.
    Type: Application
    Filed: September 6, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Haruka SAKUMA, Hidenori Miyagawa, Shosuke Fujii, Kiwamu Sakuma, Fumitaka Arai
  • Publication number: 20200303461
    Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.
    Type: Application
    Filed: September 9, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shoichi KABUYANAGI, Shosuke FUJII, Masumi SAITOH
  • Patent number: 10784312
    Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shoichi Kabuyanagi, Shosuke Fujii, Masumi Saitoh
  • Patent number: 10249818
    Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: April 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Marina Yamaguchi, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
  • Publication number: 20190088870
    Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.
    Type: Application
    Filed: March 6, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Marina YAMAGUCHI, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
  • Patent number: 10153326
    Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: December 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masato Koyama, Harumi Seki, Shosuke Fujii, Hidenori Miyagawa
  • Patent number: 10103328
    Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive layer, a second conductive layer, and an intermediate layer. The first conductive layer includes a first element. The first element includes a at least one selected from the group consisting of Ag, Cu, Ni, Co, Ti, Al, and Au. The intermediate layer is provided between the first conductive layer and the second conductive layer. The intermediate layer includes an oxide. The oxide includes a second element and a third element. The second element includes at least one second element being selected from the group consisting of Ti, Ta, Hf, W, Mg, Al, and Zr. The third element is different from the second element and includes at least one selected from the group consisting of Si, Ge, Hf, Al, Ta, W, Zr, Ti, and Mg.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Ishikawa, Harumi Seki, Shosuke Fujii, Masumi Saitoh
  • Patent number: 10096619
    Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsunehiro Ino, Shosuke Fujii, Seiji Inumiya
  • Patent number: 10038032
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 31, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kiwamu Sakuma, Shosuke Fujii, Masumi Saitoh, Toshiyuki Sasaki
  • Patent number: 9997569
    Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: June 12, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Marina Yamaguchi, Shosuke Fujii, Yuuichi Kamimuta, Takayuki Ishikawa, Masumi Saitoh
  • Patent number: 9954167
    Abstract: According to one embodiment, a memory device includes a first layer, a second layer, and a third layer provided between the first layer and the second layer. The first layer includes first interconnections and a first insulating portion. The first interconnections extend in a first direction. The first insulating portion is provided between the first interconnections. The second layer includes a plurality of second interconnections and a second insulating portion. The second interconnections extend in a second direction crossing the first direction. The second insulating portion is provided between the second interconnections. The third layer includes a ferroelectric portion and a paraelectric portion. The ferroelectric portion and the paraelectric portion include hafnium oxide.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shosuke Fujii, Takayuki Ishikawa