Abstract: A semiconductor device includes: an oxide semiconductor including a first end and a second end and extending in a first direction oriented from the second end to the first end; a first electrode configured to come into contact with the first end of the oxide semiconductor; a second electrode configured to come into contact with the second end of the oxide semiconductor; a gate electrode configured to enclose the oxide semiconductor with a first insulating film interposed therebetween between the first and second ends of the oxide semiconductor; and a metal film including a cylindrical portion that comes into contact with the gate electrode in the first direction and encloses the oxide semiconductor with the first insulating film interposed therebetween.

Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and including a first region, a second region, and a third region between the first region and the second region; a gate electrode facing the third region; a first insulating layer facing the first region; a second insulating layer facing the second region; and a gate insulating layer between the gate electrode and the oxide semiconductor layer, containing oxygen (O) and at least one metal element selected from a group consisting of Al, Hf, Zr, La, Y, Zn, In, Sn, and Ga, and having a chemical composition different from that of the oxide semiconductor layer.

Abstract: A semiconductor memory device includes a ferroelectric memory transistor. The ferroelectric memory transistor includes a first conductive layer extending in a first direction and having a cylindrical shape and an upper surface that has a diameter R1, a first semiconductor layer extending in the first direction and having a cylindrical base portion in contact with the upper surface of the first conductive layer, the cylindrical base portion extending further in a radial direction than the upper surface of the first conductive layer such that a diameter R2 thereof is greater than the diameter R1, a ferroelectric layer extending in the first direction and surrounded by the first semiconductor layer, a second conductive layer extending in the first direction and surrounded by the ferroelectric layer, and a third conductive layer in contact with an outer periphery of the first semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate, a memory capacitor provided on the semiconductor substrate, a first conductor provided above the memory capacitor and extending in a first direction, a second conductor provided above the first conductor and extending in the first direction, an oxide semiconductor layer provided between the first conductor and the second conductor and extending in the first direction, a conductive oxide layer between the second conductor and the oxide semiconductor layer, a first conductive layer between the conductive oxide layer and the second conductor, and an insulating layer in contact with the conductive oxide layer, wherein a portion of the conductive oxide layer is between and aligned with the first insulating layer and the oxide semiconductor layer in the first direction.

Abstract: A semiconductor device includes a semiconductor substrate, a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film, a second layer formed above the first layer and including a channel including an oxide semiconductor and a second insulating film, and a third layer formed above the second layer, and including an electrode formed on the channel and a third insulating film having a film density less than at least one of a film density of the first insulating film or a film density of the second insulating film.

Abstract: According to one embodiment, a semiconductor device includes a first insulating layer, a gate electrode layer provided on the first insulating layer, a second insulating layer provided on the gate electrode layer, an oxide semiconductor layer provided along the second insulating layer, the gate electrode layer and the first insulating layer, a gate insulating layer provided along the second insulating layer, the gate electrode layer and the first insulating layer, and surrounding a side surface of the oxide semiconductor layer, and a first hydrogen barrier film surrounding the oxide semiconductor layer and the gate insulating layer.

Abstract: A semiconductor device according to an embodiment includes: a first electrode; a second electrode; a gate electrode between the first electrode and the second electrode; a first insulating layer; a second insulating layer; a gate insulating layer surrounding the gate electrode; an oxide semiconductor layer surrounding the gate insulating layer, the oxide semiconductor layer including a first region between the gate insulating layer and the first electrode, a second region between the gate insulating layer and the second electrode, a third region between the gate insulating layer and the first insulating layer, and a fourth region between the gate insulating layer and the second insulating layer. A first thickness of the first region and a second thickness of the second region are equal to or less than at least one of a third thickness of the third region or a fourth thickness of the fourth region.

Abstract: A semiconductor device according to an embodiment includes a first conductor, a first oxide semiconductor, a first insulator, a second conductor, a third conductor, and a fourth conductor. The first oxide semiconductor contacts, at one end, the first conductor, and extends in a first direction intersecting a surface of the first conductor. The first insulator surrounds a side surface of the first oxide semiconductor. The second conductor and the first oxide semiconductor interpose the first insulator therebetween. The third conductor contacts another end of the first oxide semiconductor. The fourth conductor extends in a second direction intersecting the first direction, and contacts a second conductor on a side opposite to the first insulator. The second conductor is of a material with a higher work function than a material of the fourth conductor.

Abstract: A semiconductor device includes: a semiconductor substrate including a first area and a second area; a plurality of memory cells provided in the first area; a mark provided in the second area and having a first side surface and a second side surface that intersects with the first side surface; and a plurality of patterns provided in the second area and provided on the first side surface and the second side surface.

Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.

Abstract: The semiconductor memory device of the embodiment includes a stacked body including interlayer insulating layers and gate electrode layers alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a first insulating layer provided between the semiconductor layer and the gate electrode layers; conductive layers provided between the first insulating layer and the gate electrode layers; and second insulating layers provided between the conductive layers and the gate electrode layers and the second insulating layers containing ferroelectrics. Two of the conductive layers adjacent to each other in the first direction are separated by one of the interlayer insulating layers interposed between the two of the conductive layers, and a first thickness of one of the gate electrode layers in the first direction is smaller than a second thickness of one of the conductive layers in the first direction.

Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.

Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.

Abstract: The semiconductor memory device of the embodiment includes a stacked body including interlayer insulating layers and gate electrode layers alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a first insulating layer provided between the semiconductor layer and the gate electrode layers; conductive layers provided between the first insulating layer and the gate electrode layers; and second insulating layers provided between the conductive layers and the gate electrode layers and the second insulating layers containing ferroelectrics. Two of the conductive layers adjacent to each other in the first direction are separated by one of the interlayer insulating layers interposed between the two of the conductive layers, and a first thickness of one of the gate electrode layers in the first direction is smaller than a second thickness of one of the conductive layers in the first direction.

Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.

Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.

Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.

Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.

Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.

Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive layer, a second conductive layer, and an intermediate layer. The first conductive layer includes a first element. The first element includes a at least one selected from the group consisting of Ag, Cu, Ni, Co, Ti, Al, and Au. The intermediate layer is provided between the first conductive layer and the second conductive layer. The intermediate layer includes an oxide. The oxide includes a second element and a third element. The second element includes at least one second element being selected from the group consisting of Ti, Ta, Hf, W, Mg, Al, and Zr. The third element is different from the second element and includes at least one selected from the group consisting of Si, Ge, Hf, Al, Ta, W, Zr, Ti, and Mg.