Patents by Inventor Shosuke Fujii
Shosuke Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9947685Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a plurality of conductive layers, a plurality of insulating layers, an intermediate layer, and a controller. The conductive layers and the insulating layers are alternately provided. The intermediate layer is provided between the plurality of conductive layers and the semiconductor layer. The controller is configured to perform first and second operations. In first operation, the controller applies a first voltage to the semiconductor layer, applies a second voltage higher than the first voltage to a first conductive layer, and applies a third voltage to other conductive layers. In the second operation, the controller applies a fourth voltage to the semiconductor layer, applies a fifth voltage to the first conductive layer, and applies a sixth voltage to the other conductive layers.Type: GrantFiled: September 14, 2016Date of Patent: April 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shosuke Fujii, Kazuhiko Yamamoto
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Patent number: 9928908Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.Type: GrantFiled: February 6, 2017Date of Patent: March 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Reika Ichihara, Daisuke Matsushita, Shosuke Fujii
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Patent number: 9882127Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a semiconductor layer and a first layer. The first electrode includes at least one of Ag, Ni, Co, Al, Zn, Ti, and Cu. The semiconductor layer is sandwiched between the first and second electrodes. The first layer is provided between the second electrode and the semiconductor layer and contains an element included in the semiconductor layer and at least one of Ag, Ni, and Co.Type: GrantFiled: July 31, 2013Date of Patent: January 30, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shosuke Fujii, Hidenori Miyagawa, Takashi Yamauchi
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Patent number: 9865809Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.Type: GrantFiled: August 15, 2013Date of Patent: January 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hidenori Miyagawa, Akira Takashima, Shosuke Fujii
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Patent number: 9842990Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.Type: GrantFiled: December 21, 2016Date of Patent: December 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Marina Yamaguchi, Shosuke Fujii, Masumi Saitoh, Hiromichi Kuriyama, Takuya Konno
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Patent number: 9805927Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first structure having a first insulating layer, a semiconductor layer, and a second insulating layer stacked in this order in a first direction, the first structure extending in a second direction, memory cells provided on a surface of the semiconductor layer facing in a third direction, and connected in series in the second direction, and a third insulating layer contacting at least one of first and second end portions of the first structure in the second direction and not covering at least a part of an area between the first and second end portions. A lattice spacing of semiconductor atoms in the semiconductor layer in the second direction is larger than a lattice spacing of the semiconductor atoms in the semiconductor layer in the first direction.Type: GrantFiled: April 21, 2016Date of Patent: October 31, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shosuke Fujii, Kiwamu Sakuma, Masumi Saitoh
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Patent number: 9779797Abstract: A non-volatile memory device according to an embodiment includes a first conductive layer, a second conductive layer including metal nitride, the metal nitride absorbing oxygen, a paraelectric layer disposed between the first conductive layer and the second conductive layer, a ferroelectric layer disposed between the paraelectric layer and the second conductive layer, the ferroelectric layer including hafnium oxide, at least one third conductive layer disposed on opposite side of at least one of the first conductive layer and the second conductive layer to the ferroelectric layer, the at least one third conductive layer including metal oxide, the metal oxide having oxygen ratio larger than stoichiometric ratio, and a sense circuit configured to read data based on tunneling current flow between the first conductive layer and the second conductive layer through the paraelectric layer and the ferroelectric layer.Type: GrantFiled: August 24, 2016Date of Patent: October 3, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsunehiro Ino, Shosuke Fujii
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Publication number: 20170271584Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.Type: ApplicationFiled: December 21, 2016Publication date: September 21, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Marina YAMAGUCHI, Shosuke Fujii, Masumi Saitoh, Hiromichi Kuriyama, Takuya Konno
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Publication number: 20170271585Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive layer, a second conductive layer, and an intermediate layer. The first conductive layer includes a first element. The first element includes a at least one selected from the group consisting of Ag, Cu, Ni, Co, Ti, Al, and Au. The intermediate layer is provided between the first conductive layer and the second conductive layer. The intermediate layer includes an oxide. The oxide includes a second element and a third element. The second element includes at least one second element being selected from the group consisting of Ti, Ta, Hf, W, Mg, Al, and Zr. The third element is different from the second element and includes at least one selected from the group consisting of Si, Ge, Hf, Al, Ta, W, Zr, Ti, and Mg.Type: ApplicationFiled: December 21, 2016Publication date: September 21, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takayuki ISHIKAWA, Harumi SEKI, Shosuke FUJII, Masumi SAITOH
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Publication number: 20170271360Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a plurality of conductive layers, a plurality of insulating layers, an intermediate layer, and a controller. The conductive layers and the insulating layers are alternately provided. The intermediate layer is provided between the plurality of conductive layers and the semiconductor layer. The controller is configured to perform first and second operations. In first operation, the controller applies a first voltage to the semiconductor layer, applies a second voltage higher than the first voltage to a first conductive layer, and applies a third voltage to other conductive layers. In the second operation, the controller applies a fourth voltage to the semiconductor layer, applies a fifth voltage to the first conductive layer, and applies a sixth voltage to the other conductive layers.Type: ApplicationFiled: September 14, 2016Publication date: September 21, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shosuke FUJII, Kazuhiko Yamamoto
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Patent number: 9761798Abstract: A storage device of an embodiment includes a first conductive layer containing a first element selected from the group consisting of Si, Ge, and a metal element, a second conductive layer including a first region containing a first metal element and carbon or nitrogen, a second region containing a second metal element and carbon or nitrogen, and a third region provided between the first region and the second region, the third region containing a third metal element, the standard free energy of formation of an oxide of the third metal element being smaller than the standard free energy of formation of an oxide of the first element, a ferroelectric layer provided between the first conductive layer and the second conductive layer, and a paraelectric layer provided between the first conductive layer and the ferroelectric layer.Type: GrantFiled: March 7, 2016Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuuichi Kamimuta, Shosuke Fujii, Masumi Saitoh
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Patent number: 9680094Abstract: According to one embodiment, a memory device includes a first electrode, a first resistance change layer, a first insulating section, a second electrode and an intermediate layer. The first resistance change layer is provided on the first electrode. The first insulating section is provided on the first resistance change layer. The second electrode is provided on the first resistance change layer. The second electrode is in contact with the first resistance change layer. The intermediate layer is provided between the second electrode and the first insulating section. The intermediate layer is in contact with the second electrode and the first insulating section.Type: GrantFiled: December 17, 2012Date of Patent: June 13, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shosuke Fujii, Takashi Haimoto
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Publication number: 20170148516Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.Type: ApplicationFiled: February 6, 2017Publication date: May 25, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Reika ICHIHARA, Daisuke MATSUSHITA, Shosuke FUJII
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Patent number: 9634248Abstract: According to one embodiment, an insulator includes a material including barium and hafnium oxide. The material has a crystal structure of a space group Pbc21.Type: GrantFiled: March 4, 2016Date of Patent: April 25, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Yasushi Nakasaki, Shosuke Fujii, Daisuke Matsushita
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Patent number: 9601192Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.Type: GrantFiled: February 12, 2015Date of Patent: March 21, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Reika Ichihara, Daisuke Matsushita, Shosuke Fujii
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Publication number: 20170069841Abstract: According to one embodiment, an insulator includes a material including barium and hafnium oxide. The material has a crystal structure of a space group Pbc21.Type: ApplicationFiled: March 4, 2016Publication date: March 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Yasushi NAKASAKI, Shosuke FUJII, Daisuke MATSUSHITA
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Publication number: 20170040380Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.Type: ApplicationFiled: August 3, 2016Publication date: February 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Marina YAMAGUCHI, Shosuke FUJII, Yuuichi KAMIMUTA, Takayuki ISHIKAWA, Masumi SAITOH
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Publication number: 20170033118Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first structure having a first insulating layer, a semiconductor layer, and a second insulating layer stacked in this order in a first direction, the first structure extending in a second direction, memory cells provided on a surface of the semiconductor layer facing in a third direction, and connected in series in the second direction, and a third insulating layer contacting at least one of first and second end portions of the first structure in the second direction and not covering at least a part of an area between the first and second end portions. A lattice spacing of semiconductor atoms in the semiconductor layer in the second direction is larger than a lattice spacing of the semiconductor atoms in the semiconductor layer in the first direction.Type: ApplicationFiled: April 21, 2016Publication date: February 2, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shosuke FUJII, Kiwamu SAKUMA, Masumi SAITOH
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Publication number: 20170005261Abstract: According to one embodiment, a memory device includes a first layer, a second layer, and a third layer provided between the first layer and the second layer. The first layer includes first interconnections and a first insulating portion. The first interconnections extend in a first direction. The first insulating portion is provided between the first interconnections. The second layer includes a plurality of second interconnections and a second insulating portion. The second interconnections extend in a second direction crossing the first direction. The second insulating portion is provided between the second interconnections. The third layer includes a ferroelectric portion and a paraelectric portion. The ferroelectric portion and the paraelectric portion include hafnium oxide.Type: ApplicationFiled: September 15, 2016Publication date: January 5, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shosuke FUJII, Takayuki ISHIKAWA
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Publication number: 20160372478Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.Type: ApplicationFiled: September 6, 2016Publication date: December 22, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Shosuke FUJII, Seiji INUMIYA