Abstract: A non-volatile memory device according to an embodiment includes a first conductive layer, a second conductive layer including metal nitride, the metal nitride absorbing oxygen, a paraelectric layer disposed between the first conductive layer and the second conductive layer, a ferroelectric layer disposed between the paraelectric layer and the second conductive layer, the ferroelectric layer including hafnium oxide, at least one third conductive layer disposed on opposite side of at least one of the first conductive layer and the second conductive layer to the ferroelectric layer, the at least one third conductive layer including metal oxide, the metal oxide having oxygen ratio larger than stoichiometric ratio, and a sense circuit configured to read data based on tunneling current flow between the first conductive layer and the second conductive layer through the paraelectric layer and the ferroelectric layer.

Abstract: A storage device of an embodiment includes a first conductive layer containing a first element selected from the group consisting of Si, Ge, and a metal element, a second conductive layer including a first region containing a first metal element and carbon or nitrogen, a second region containing a second metal element and carbon or nitrogen, and a third region provided between the first region and the second region, the third region containing a third metal element, the standard free energy of formation of an oxide of the third metal element being smaller than the standard free energy of formation of an oxide of the first element, a ferroelectric layer provided between the first conductive layer and the second conductive layer, and a paraelectric layer provided between the first conductive layer and the ferroelectric layer.

Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a variable resistance layer. The variable resistance layer is provided between the first electrode and the second electrode. The variable resistance layer contains impurity of a nonmetallic element. The impurity is at least one selected from the group consisting of S, Se, Te, F, Cl, Br, and I.

Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.

Abstract: According to one embodiment, a resistive random access memory device includes a first wiring extending in a first direction, a first ion source layer provided in a first portion on the first wiring and a first variable resistance layer provided on the first ion source layer. The resistive random access memory device also includes a second wiring, which is provided on the first variable resistance layer, faces the first portion, and extends in a second direction different from the first direction. The resistive random access memory device also includes a second variable resistance layer provided in a second portion on the second wiring, a second ion source layer provided on the second variable resistance layer and a third wiring, which is provided on the second ion source layer, faces the second portion, and extends in the first direction.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a first layer and a second layer. The second electrode contains at least one metal element selected from Ag, Cu, Ni, Co, Al, and Ti. The first layer is arranged between the first electrode and the second electrode. The second layer is arranged between the first electrode and the first layer. A diffusion coefficient of the metal element in the second layer is larger than a diffusion coefficient of the metal element in the first layer.

Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to nth semiconductor layers (n is a natural number greater than or equal to 2) stacked in a first direction, and extending in a second direction, and first to nth memory cells provided on surfaces of the first to nth semiconductor layers facing a third direction. The ith memory cell (1?i?n) comprises a second stacked layer structure in which a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode are stacked. The second insulating layer has an equivalent oxide thickness smaller than that of the first insulating layer.

Abstract: According to one embodiment, a nonvolatile memory device includes a first metal layer, a second metal layer, a first layer, a second layer, and a third layer. The first metal layer contains at least one first metal selected from the group consisting of Al, Ni, Ti, Co, Mg, Cr, Mn, Zn, and In. The second metal layer contains at least one second metal selected from the group consisting of Ag, Cu, Fe, Sn, Pb, and Bi. The first layer is provided between the first metal layer and the second metal layer, and contains a first oxide. The second layer is provided between the first layer and the second metal layer, and contains a second oxide. The third layer is provided between the first layer and the second layer, and contains one of a silicon oxide, a silicon nitride, and a silicon oxynitride.

Abstract: A semiconductor memory device according to an embodiment comprises a memory cell and a control circuit, the control circuit performing write of data to the memory cell. The memory cell includes a second resistance varying layer sandwiched between a first resistance varying layer and a third resistance varying layer. The second resistance varying layer has a resistance value which is smaller than that of the other resistance varying layers. The control circuit applies to the memory cell a first voltage pulse, and then applies to the memory cell a second voltage pulse that has a rise time which is shorter than that of the first voltage pulse.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to nth semiconductor layers (n is a natural number greater than or equal to 2) stacked in a first direction, and extending in a second direction, and first to nth memory cells provided on surfaces of the first to nth semiconductor layers facing a third direction. The ith memory cell (1?i?n) comprises a second stacked layer structure in which a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode are stacked. The second insulating layer has an equivalent oxide thickness smaller than that of the first insulating layer.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to nth semiconductor layers (n is a natural number greater than or equal to 2) stacked in a first direction, and extending in a second direction, and first to nth memory cells provided on surfaces of the first to nth semiconductor layers facing a third direction. The ith memory cell (1?i?n) comprises a second stacked layer structure in which a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode are stacked. The second insulating layer has an equivalent oxide thickness smaller than that of the first insulating layer.

Abstract: According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode.

Abstract: A memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Abstract: A non-volatile memory device of an embodiment includes: a first conductive layer; a second conductive layer; a ferroelectric film provided between the first conductive layer and the second conductive layer; and a paraelectric film provided between one of the first conductive layer and the second conductive layer, and the ferroelectric film, the paraelectric film having film thickness of 1.5 nm or more and 10 nm or less, and the paraelectric film having a dielectric constant higher than the ferroelectric film.

Abstract: A memory device according to an embodiment, includes a substrate, two or more resistance change memory cells stacked on the substrate, two or more transistors stacked on the substrate, and two or more wirings stacked on the substrate. One of the memory cells and one of the transistors are connected to each other via one of the wirings.

Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.