Patents by Inventor Shosuke Fujii
Shosuke Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8916848Abstract: According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode.Type: GrantFiled: August 29, 2012Date of Patent: December 23, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shosuke Fujii, Daisuke Matsushita, Yuichiro Mitani
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Publication number: 20140353572Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: ApplicationFiled: August 14, 2014Publication date: December 4, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Riichiro Takaishi, Hidenori Miyagawa, Shosuke Fujii
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Publication number: 20140346434Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hidenori MIYAGAWA, Shosuke FUJII, Akira TAKASHIMA, Daisuke MATSUSHITA
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Patent number: 8860182Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: GrantFiled: September 6, 2013Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Riichiro Takaishi, Hidenori Miyagawa, Shosuke Fujii
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Patent number: 8854874Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: GrantFiled: August 14, 2013Date of Patent: October 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20140284543Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode, and a variable resistance portion placed between the first electrode and the second electrode. The variable resistance portion includes a first insulating layer, a second insulating layer, and a crystal layer that is placed between the first insulating layer and the second insulating layer, has a higher resistivity than the first electrode, and is crystalline.Type: ApplicationFiled: September 10, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Takayuki Ishikawa, Shosuke Fujii, Hidenori Miyagawa, Hiroki Tanaka, Masumi Saitoh
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Publication number: 20140284544Abstract: A resistance random access memory device according an embodiment includes a first electrode, a second electrode and a resistance change layer. The first electrode includes a metal. The resistance change layer is provided between the first electrode and the second electrode. One of the metal is able to reversibly move within the resistance change layer. The second electrode is formed of a material ionizing less easily than the metal. The resistance change layer contains silicon, oxygen, and nitrogen, a nitrogen concentration of the resistance change layer is less than 46 atomic % and not less than 20 atomic %.Type: ApplicationFiled: September 10, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hidenori MIYAGAWA, Shosuke FUJII, Takayuki ISHIKAWA
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Publication number: 20140284535Abstract: A memory device according to an embodiment, includes a substrate, two or more resistance change memory cells stacked on the substrate, two or more transistors stacked on the substrate, and two or more wirings stacked on the substrate. One of the memory cells and one of the transistors are connected to each other via one of the wirings.Type: ApplicationFiled: July 24, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Takayuki Ishikawa, Shosuke Fujii, Kiyohito Nishihara
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Publication number: 20140284541Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: ApplicationFiled: September 6, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Riichiro TAKAISHI, Hidenori Miyagawa, Shosuke Fujii
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Patent number: 8835896Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: GrantFiled: August 19, 2013Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hidenori Miyagawa, Shosuke Fujii, Akira Takashima, Daisuke Matsushita
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Publication number: 20140191184Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.Type: ApplicationFiled: March 13, 2014Publication date: July 10, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Takashi YAMAUCHI, Shosuke Fujii, Reika Ichihara
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Patent number: 8710580Abstract: According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.Type: GrantFiled: November 29, 2012Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kiwamu Sakuma, Haruka Kusai, Shosuke Fujii, Li Zhang, Masahiro Kiyotoshi, Masao Shingu
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Patent number: 8698277Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.Type: GrantFiled: September 15, 2011Date of Patent: April 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamauchi, Shosuke Fujii, Reika Ichihara
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Patent number: 8698313Abstract: A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al2O3, HfO2, ZrO2, TiO2, and MgO, the material is stoichiometric composition, and the charge trapping film includes material different from the material of the metal oxide.Type: GrantFiled: April 26, 2012Date of Patent: April 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Izumi Hirano, Shosuke Fujii, Yuichiro Mitani, Naoki Yasuda
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Publication number: 20140070160Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a variable resistance layer. The variable resistance layer is provided between the first electrode and the second electrode. The variable resistance layer contains impurity of a nonmetallic element. The impurity is at least one selected from the group consisting of S, Se, Te, F, Cl, Br, and I.Type: ApplicationFiled: December 14, 2012Publication date: March 13, 2014Inventors: Takayuki ISHIKAWA, Yoshifumi NISHI, Shosuke FUJII
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Publication number: 20140061570Abstract: According to one embodiment, a memory device includes a first electrode, a first resistance change layer, a first insulating section, a second electrode and an intermediate layer. The first resistance change layer is provided on the first electrode. The first insulating section is provided on the first resistance change layer. The second electrode is provided on the first resistance change layer. The second electrode is in contact with the first resistance change layer. The intermediate layer is provided between the second electrode and the first insulating section. The intermediate layer is in contact with the second electrode and the first insulating section.Type: ApplicationFiled: December 17, 2012Publication date: March 6, 2014Inventors: Shosuke FUJII, Takashi Haimoto
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Patent number: 8664632Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.Type: GrantFiled: August 30, 2012Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Shosuke Fujii, Yoshifumi Nishi, Akira Takashima, Takayuki Ishikawa, Hidenori Miyagawa, Takashi Haimoto, Yusuke Arayashiki, Hideki Inokuma
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Publication number: 20140003130Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.Type: ApplicationFiled: September 3, 2013Publication date: January 2, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Reika ICHIHARA, Daisuke Matsushita, Shosuke Fujii
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Patent number: 8610101Abstract: According to one embodiment, there are provided a first electrode, a second electrode containing a 1B group element having an Al element added thereto, and a variable resistive layer disposed between the first electrode and the second electrode and having a silicon element.Type: GrantFiled: January 27, 2012Date of Patent: December 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamauchi, Shosuke Fujii, Reika Ichihara
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Publication number: 20130328009Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: ApplicationFiled: August 19, 2013Publication date: December 12, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hidenori MIYAGAWA, Shosuke Fujii, Akira Takashima, Daisuke Matsushita