Patents by Inventor Shosuke Fujii
Shosuke Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9147469Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: GrantFiled: January 22, 2015Date of Patent: September 29, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Akira Takashima, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20150255479Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to nth semiconductor layers (n is a natural number greater than or equal to 2) stacked in a first direction, and extending in a second direction, and first to nth memory cells provided on surfaces of the first to nth semiconductor layers facing a third direction. The ith memory cell (1?i?n) comprises a second stacked layer structure in which a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode are stacked. The second insulating layer has an equivalent oxide thickness smaller than that of the first insulating layer.Type: ApplicationFiled: September 18, 2014Publication date: September 10, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kiwamu SAKUMA, Masahiro KIYOTOSHI, Shosuke FUJII
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Patent number: 9117848Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin structure stacked in order of a first oxide layer, a semiconductor layer and a second oxide layer in a first direction perpendicular to a surface of the semiconductor substrate, the fin structure extending in a second direction parallel to the surface of the semiconductor substrate, and a gate structure stacked in order of a gate oxide layer, a charge storage layer, a block insulating layer and a control gate electrode in a third direction perpendicular to the first and second directions from a surface of the semiconductor layer in the third direction.Type: GrantFiled: January 29, 2013Date of Patent: August 25, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Haruka Kusai, Kiwamu Sakuma, Masao Shingu, Shosuke Fujii, Masahiro Kiyotoshi
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Patent number: 9099645Abstract: A resistance random access memory device according an embodiment includes a first electrode, a second electrode and a resistance change layer. The first electrode includes a metal. The resistance change layer is provided between the first electrode and the second electrode. One of the metal is able to reversibly move within the resistance change layer. The second electrode is formed of a material ionizing less easily than the metal. The resistance change layer contains silicon, oxygen, and nitrogen, a nitrogen concentration of the resistance change layer is less than 46 atomic % and not less than 20 atomic %.Type: GrantFiled: September 10, 2013Date of Patent: August 4, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hidenori Miyagawa, Shosuke Fujii, Takayuki Ishikawa
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Patent number: 9087715Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.Type: GrantFiled: July 12, 2012Date of Patent: July 21, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Haruka Kusai, Kiwamu Sakuma, Shosuke Fujii, Masumi Saitoh, Masahiro Kiyotoshi
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Patent number: 9082973Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode, and a variable resistance portion placed between the first electrode and the second electrode. The variable resistance portion includes a first insulating layer, a second insulating layer, and a crystal layer that is placed between the first insulating layer and the second insulating layer, has a higher resistivity than the first electrode, and is crystalline.Type: GrantFiled: September 10, 2013Date of Patent: July 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ishikawa, Shosuke Fujii, Hidenori Miyagawa, Hiroki Tanaka, Masumi Saitoh
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Patent number: 9053786Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.Type: GrantFiled: September 3, 2013Date of Patent: June 9, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Reika Ichihara, Daisuke Matsushita, Shosuke Fujii
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Publication number: 20150155035Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.Type: ApplicationFiled: February 12, 2015Publication date: June 4, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Reika ICHIHARA, Daisuke MATSUSHITA, Shosuke FUJII
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Patent number: 9040949Abstract: According to one embodiment, an information recording device includes first and second electrodes, a variable resistance layer between the first and second electrodes, and a control circuit which controls the variable resistance layer to n (n is a natural number except 1) kinds of resistance. The variable resistance layer comprises a material filled between the first and second electrodes, and particles arranged in a first direction from the first electrode to the second electrode in the material, and each of the particles has a resistance lower than that of the material. A resistance of the variable resistance layer is decided by a short between the first electrode and at least one of the particles.Type: GrantFiled: March 18, 2011Date of Patent: May 26, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yuichiro Mitani, Daisuke Matsushita, Shosuke Fujii
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Publication number: 20150131363Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: ApplicationFiled: January 22, 2015Publication date: May 14, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira TAKASHIMA, Hidenori MIYAGAWA, Shosuke FUJII, Daisuke MATSUSHITA
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Patent number: 9024287Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and an insulating portion. The first electrode includes an ionizable metal. The second electrode includes a conductive material. The conductive material is more difficult to ionize than the metal. The insulating portion is provided between the first electrode and the second electrode. The insulating portion is made of an insulating material. A space is adjacent to a side surface of the insulating portion between the first electrode and the second electrode.Type: GrantFiled: August 7, 2014Date of Patent: May 5, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ishikawa, Hiroki Tanaka, Shosuke Fujii
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Publication number: 20150102279Abstract: According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode.Type: ApplicationFiled: November 21, 2014Publication date: April 16, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shosuke FUJII, Daisuke MATSUSHITA, Yuichiro MITANI
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Patent number: 8987807Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.Type: GrantFiled: September 19, 2012Date of Patent: March 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shosuke Fujii, Kiwamu Sakuma, Jun Fujiki, Atsuhiro Kinoshita
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Publication number: 20150078063Abstract: A semiconductor memory device according to an embodiment comprises a memory cell and a control circuit, the control circuit performing write of data to the memory cell. The memory cell includes a second resistance varying layer sandwiched between a first resistance varying layer and a third resistance varying layer. The second resistance varying layer has a resistance value which is smaller than that of the other resistance varying layers. The control circuit applies to the memory cell a first voltage pulse, and then applies to the memory cell a second voltage pulse that has a rise time which is shorter than that of the first voltage pulse.Type: ApplicationFiled: July 28, 2014Publication date: March 19, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Reika ICHIHARA, Shosuke FUJII, Hidenori MIYAGAWA, Takayuki ISHIKAWA
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Publication number: 20150076439Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.Type: ApplicationFiled: July 30, 2014Publication date: March 19, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Masumi SAITOH, Takayuki ISHIKAWA, Shosuke FUJII, Hidenori MIYAGAWA, Chika TANAKA, Ichiro MIZUSHIMA
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Publication number: 20150076440Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and an insulating portion. The first electrode includes an ionizable metal. The second electrode includes a conductive material. The conductive material is more difficult to ionize than the metal. The insulating portion is provided between the first electrode and the second electrode. The insulating portion is made of an insulating material. A space is adjacent to a side surface of the insulating portion between the first electrode and the second electrode.Type: ApplicationFiled: August 7, 2014Publication date: March 19, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Takayuki ISHIKAWA, Hiroki Tanaka, Shosuke Fujii
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Patent number: 8981461Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction.Type: GrantFiled: September 19, 2012Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shosuke Fujii, Daisuke Hagishima, Kiwamu Sakuma
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Patent number: 8975611Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.Type: GrantFiled: March 13, 2014Date of Patent: March 10, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamauchi, Shosuke Fujii, Reika Ichihara
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Patent number: 8971106Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: GrantFiled: September 8, 2014Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20140376303Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira TAKASHIMA, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita