Patents by Inventor Shriram Shivaraman

Shriram Shivaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031503
    Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Publication number: 20210167073
    Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Shriram Shivaraman, Seung Hoon Sung, Ashish Verma Penumatcha, Uygar E. Avci
  • Publication number: 20210167182
    Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Seung Hoon SUNG, Ashish Verma PENUMATCHA, Sou-Chi CHANG, Devin MERRILL, I-Cheng TUNG, Nazila HARATIPOUR, Jack T. KAVALIEROS, Ian A. YOUNG, Matthew V. METZ, Uygar E. AVCI, Chia-Ching LIN, Owen LOH, Shriram SHIVARAMAN, Eric Charles MATTSON
  • Patent number: 11011550
    Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Van Le, Abhishek Sharma, Gilbert Dewey, Ravi Pillarisetty, Shriram Shivaraman, Tahir Ghani, Jack Kavalieros
  • Patent number: 11004982
    Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Van H. Le, Abhishek A. Sharma, Ravi Pillarisetty, Gilbert W. Dewey, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Tahir Ghani
  • Publication number: 20210111179
    Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Shriram SHIVARAMAN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Nazila HARATIPOUR, Uygar E. AVCI
  • Patent number: 10964701
    Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Anil Sharma, Van H. Le, Gilbert William Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 10930679
    Abstract: Thin film transistors (TFTs) including a channel and source/drain that comprise an oxide semiconductor. Oxide semiconductor within the source/drain may be more ordered than the oxide semiconductor within the channel. The localized increased order of the oxide semiconductor may reduce TFT access resistance while retaining good channel gating properties. In some embodiments, order within the source or drain templates from order in adjacent contact metallization. Contact metal at the interface of the oxide semiconductor may be chosen to promote grain growth in the oxide semiconductor during deposition of the oxide semiconductor, or through solid phase epitaxy of the oxide semiconductor subsequent to deposition. Where TFT circuitry is integrated into the BEOL of a CMOS FET IC fabrication process, an EOL forming gas anneal may be employed to both passivate CMOS FETs and crystalize a source/drain of the TFTs.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek A. Sharma, Shriram Shivaraman, Van H. Le, Ravi Pillarisetty, Tahir Ghani
  • Patent number: 10930791
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Van H. Le, Rafael Rios, Shriram Shivaraman, Jack T. Kavalieros, Marko Radosavljevic
  • Publication number: 20200411692
    Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
  • Publication number: 20200357929
    Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.
    Type: Application
    Filed: September 29, 2017
    Publication date: November 12, 2020
    Applicant: INTEL CORPORATION
    Inventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
  • Publication number: 20200343379
    Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 27, 2017
    Publication date: October 29, 2020
    Inventors: Abhishek A. SHARMA, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Gilbert DEWEY, Shriram SHIVARAMAN, Inanc MERIC, Benjamin CHU-KUNG
  • Publication number: 20200312973
    Abstract: This disclosure illustrates a transistor with dual gate workfunctions. The transistor with dual gate workfunctions may comprise a source region, a drain region, a channel between the source region and the drain region, and a gate to control a conductivity of the channel. The gate may comprise a first portion with a first workfunction and a second portion with a second workfunction. One of the portions is nearer the source region than the other portion. The workfunction of the portion nearer the source provides a lower thermionic barrier than the workfunction of the portion further away from the source.
    Type: Application
    Filed: December 21, 2017
    Publication date: October 1, 2020
    Inventors: Sean T. MA, Abhishek SHARMA, Gilbert DEWEY, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Benjamin CHU-KUNG, Shriram SHIVARAMAN
  • Publication number: 20200227568
    Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Inventors: Van H. LE, Abhishek A. SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Ravi PILLARISETTY, Miriam R. RESHOTKO, Shriram SHIVARAMAN, Li Huey TAN, Tristan A. TRONIC, Jack T. KAVALIEROS
  • Publication number: 20200220024
    Abstract: A back-gated thin-film transistor (TFT) includes a gate electrode, a gate dielectric on the gate electrode, an active layer on the gate dielectric and having source and drain regions and a semiconductor region physically connecting the source and drain regions, a capping layer on the semiconductor region, and a charge trap layer on the capping layer. In an embodiment, a memory cell includes this back-gated TFT and a capacitor, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline, the capacitor having a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In another embodiment, an embedded memory includes wordlines extending in a first direction, bitlines extending in a second direction crossing the first direction, and several such memory cells at crossing regions of the wordlines and bitlines.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Cory E. Weber, Sean T. Ma, Tahir Ghani, Shriram Shivaraman, Gilbert Dewey
  • Publication number: 20200185504
    Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.
    Type: Application
    Filed: September 27, 2017
    Publication date: June 11, 2020
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey, Shriram Shivaraman, Sean T. Ma, Benjamin Chu-Kung
  • Publication number: 20200152635
    Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 31, 2017
    Publication date: May 14, 2020
    Inventors: ABHISHEK A. SHARMA, VAN H. LE, GILBERT DEWEY, SHRIRAM SHIVARAMAN, YIH WANG, TAHIR GHANI, JACK T. KAVALIEROS
  • Patent number: 10644123
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Van H. Le, Rafael Rios, Jack T. Kavalieros, Shriram Shivaraman
  • Publication number: 20200127142
    Abstract: Thin film core-shell fin and nanowire transistors are described. In an example, an integrated circuit structure includes a fin on an insulator layer above a substrate. The fin has a top and sidewalls. The fin is composed of a first semiconducting oxide material. A second semiconducting oxide material is on the top and sidewalls of the fin. A gate electrode is over a first portion of the second semiconducting oxide material on the top and sidewalls of the fin. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact over a second portion of the second semiconducting oxide material on the top and sidewalls of the fin. A second conductive contact is adjacent the second side of the gate electrode, the second conductive contact over a third portion of the second semiconducting oxide material on the top and sidewalls of the fin.
    Type: Application
    Filed: June 20, 2017
    Publication date: April 23, 2020
    Inventors: Gilbert DEWEY, Van H. LE, Abhishek A. SHARMA, Shriram SHIVARAMAN, Ravi PILLARISETTY, Tahir GHANI, Jack T. KAVALIEROS
  • Publication number: 20200105892
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Nazila HARATIPOUR, Tahir GHANI, Jack T. KAVALIEROS, Gilbert DEWEY, Benjamin CHU-KUNG, Seung Hoon SUNG, Van H. LE, Shriram SHIVARAMAN, Abhishek SHARMA