Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.

Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.

Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors.

Abstract: Thin film transistors (TFTs) including a channel and source/drain that comprise an oxide semiconductor. Oxide semiconductor within the source/drain may be more ordered than the oxide semiconductor within the channel. The localized increased order of the oxide semiconductor may reduce TFT access resistance while retaining good channel gating properties. In some embodiments, order within the source or drain templates from order in adjacent contact metallization. Contact metal at the interface of the oxide semiconductor may be chosen to promote grain growth in the oxide semiconductor during deposition of the oxide semiconductor, or through solid phase epitaxy of the oxide semiconductor subsequent to deposition. Where TFT circuitry is integrated into the BEOL of a CMOS FET IC fabrication process, an EOL forming gas anneal may be employed to both passivate CMOS FETs and crystalize a source/drain of the TFTs.

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

Abstract: This disclosure illustrates a transistor with dual gate workfunctions. The transistor with dual gate workfunctions may comprise a source region, a drain region, a channel between the source region and the drain region, and a gate to control a conductivity of the channel. The gate may comprise a first portion with a first workfunction and a second portion with a second workfunction. One of the portions is nearer the source region than the other portion. The workfunction of the portion nearer the source provides a lower thermionic barrier than the workfunction of the portion further away from the source.

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

Abstract: A back-gated thin-film transistor (TFT) includes a gate electrode, a gate dielectric on the gate electrode, an active layer on the gate dielectric and having source and drain regions and a semiconductor region physically connecting the source and drain regions, a capping layer on the semiconductor region, and a charge trap layer on the capping layer. In an embodiment, a memory cell includes this back-gated TFT and a capacitor, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline, the capacitor having a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In another embodiment, an embedded memory includes wordlines extending in a first direction, bitlines extending in a second direction crossing the first direction, and several such memory cells at crossing regions of the wordlines and bitlines.

Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors.

Abstract: Thin film core-shell fin and nanowire transistors are described. In an example, an integrated circuit structure includes a fin on an insulator layer above a substrate. The fin has a top and sidewalls. The fin is composed of a first semiconducting oxide material. A second semiconducting oxide material is on the top and sidewalls of the fin. A gate electrode is over a first portion of the second semiconducting oxide material on the top and sidewalls of the fin. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact over a second portion of the second semiconducting oxide material on the top and sidewalls of the fin. A second conductive contact is adjacent the second side of the gate electrode, the second conductive contact over a third portion of the second semiconducting oxide material on the top and sidewalls of the fin.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, where the channel layer includes a first region and a second region, and the first region has a first dopant concentration. A gate electrode is above the first region of the channel layer and separated from the channel layer by a gate dielectric layer. A spacer is next to the gate electrode to separate the gate electrode from a drain electrode or a source electrode above the channel layer. The spacer includes a dopant material in contact with the second region of the channel layer, and the second region has a second dopant concentration different from the first dopant concentration in the first region. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.