Patents by Inventor Shu Lin

Shu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210287944
    Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 16, 2021
    Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
  • Publication number: 20210280491
    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Tsung-Shu Lin, Wensen Hung, Hung-Chi Li, Tsung-Yu Chen
  • Patent number: 11114981
    Abstract: Disclosed is a differential amplifier including an input circuit, a detecting and controlling circuit, and an output circuit. The input circuit outputs input current to two output nodes according to the voltage of a differential input signal and the voltage of a bias node. The detecting and controlling circuit outputs compensative current to the two output nodes according to control bias voltage and the voltage of the bias node, in which the voltage of the bias node and the compensative current relate to the voltage of the differential input signal. The output circuit is coupled to the two output nodes and outputs a differential output signal according to the sum of the input current and the compensative current. Due to the detecting and controlling circuit outputting the compensative current, the differential amplifier prevents itself from entering a deadlock state even though the input current is insufficient or zero.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: September 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Tzung-Ling Tsai, Shu-Lin Chang, Chih-Lung Chen
  • Publication number: 20210272875
    Abstract: In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Yuan Sheng Chiu, Chih-Kai Cheng, Tsung-Shu Lin
  • Publication number: 20210273047
    Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.
    Type: Application
    Filed: July 21, 2020
    Publication date: September 2, 2021
    Inventors: Shu KUAN, Shahaji B. MORE, Chien LIN, Cheng-Han LEE, Shih-Chieh CHANG
  • Patent number: 11105928
    Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×1015 cm?3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: August 31, 2021
    Assignee: Artilux, Inc.
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Shu-Lu Chen, Yun-Chung Na, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang, Jung-Chin Chiang, Yen-Cheng Lu, Yen-Ju Lin
  • Patent number: 11101429
    Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
  • Patent number: 11099879
    Abstract: In one example, a system for executing applications can include a main processor to initialize a virtual machine to execute an application. The main processor can also determine a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture. Additionally, the main processor can transmit an instruction from the application to the auxiliary processor for execution and update context data for the application in response to receiving an execution result from the auxiliary processor.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Tianyou Li, Shu Xu, Jinkui Ren, Zidong Jiang, Weiliang Lin, Chaobo Zhu, Yong Hu
  • Patent number: 11095612
    Abstract: Techniques for providing flow meta data exchanges between network and security functions for a security service are disclosed. In some embodiments, a system/process/computer program product for providing flow meta data exchanges between network and security functions for a security service includes receiving a flow at a network gateway of a security service from a software-defined wide area network (SD-WAN) device; inspecting the flow to determine meta information associated with the flow; and communicating the meta information associated with the flow to the SD-WAN device.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 17, 2021
    Assignee: Palo Alto Networks, Inc.
    Inventors: Anand Oswal, Arivu Mani Ramasamy, Bhaskar Bhupalam, Shu Lin
  • Patent number: 11088048
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hsi Wu, Wensen Hung, Tsung-Shu Lin, Shih-Chang Ku, Tsung-Yu Chen, Hung-Chi Li
  • Patent number: 11088079
    Abstract: A package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Kai Cheng, Tsung-Shu Lin, Tsung-Yu Chen, Hsien-Pin Hu, Wen-Hsin Wei
  • Publication number: 20210233833
    Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Patent number: 11069642
    Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. The redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. The conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. The first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Hsuan-Ning Shih
  • Patent number: 11062971
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 11062953
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
  • Publication number: 20210193550
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Shu Lin, Tsung-Yu Chen, Chien-Yuan Huang, Chen-Hsiang Lao
  • Publication number: 20210186817
    Abstract: A permeable spraying device for making drug tablets mainly comprises a carrying platform, a spraying equipment, a flattening device and a control equipment, the carrying platform defines a powder dropping area and a flattened spraying area, and a moving device combined with the carrying platform is capable of moving vertically. The spraying equipment is mounted above the carrying platform, and the spraying equipment comprises a powder box, a colloid spraying equipment, a driving device and a placement platform. The placement platform is disposed with a plurality of supplementary colloid carriers. The flattening device is installed on the carrying platform and moves horizontally back and forth in the flattened spraying area. The control equipment is equipped with a storage unit and an execution control unit. A multi-layer drug body structure can be formed by deposition, stacking and bonding.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 24, 2021
    Inventors: Kuo-Ming HUANG, Yen-Shu LIN, Yen-Chao YANG, Yao-Jen LIANG
  • Patent number: 11038530
    Abstract: Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT).
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: June 15, 2021
    Assignee: WESTHOLD CORPORATION
    Inventors: Shu Lin, Khaled Ahmed Sabry Abdel-Ghaffar, Juane Li, Keke Liu
  • Publication number: 20210175191
    Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
  • Patent number: D928872
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Hopax Chemicals Mfg. Co., Ltd.
    Inventors: Mei-Lin Kuo, Tzu-Jung Wang, Kai-Wei Shih, Shu-Wei Ho