Patents by Inventor Shu Lin

Shu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12385810
    Abstract: A device for in-situ measurement of substance migration and transformation on a sediment-water interface includes a floating platform. Three take-up and pay-off components are fixedly connected to the edge of a top surface of the floating platform. Each take-up and pay-off component comprises an L-shaped base, a cable take-up and pay-off assembly, vertical rods, a guide sheave wheel, an adjustment assembly and a first cable. Two DGT samplers are fixedly connected to bottom ends of two three take-up and pay-off components. Water quality monitoring sensors are fixedly connected to the two first cables fixedly connected to the two DGT samplers, respectively. A sediment collector is fixedly connected to a bottom end of the other take-up and pay-off component. Sampling can be performed in-situ directly through DGT flat plates to avoid the impact of environmental changes.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: August 12, 2025
    Assignee: SOUTH CHINA INSTITUTE OF ENVIRONMENTAL SCIENCE, MEE (ECOLOGICAL AND ENVIRONMENTAL EMERGENCY RESEARCH INSTITUTE, MEE)
    Inventors: Weijie Li, Shu Lin, Jiale Chen, Runmian Yang, Huaiyang Fang, Xiaobao Li
  • Publication number: 20250241038
    Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.
    Type: Application
    Filed: April 8, 2025
    Publication date: July 24, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Patent number: 12327819
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: June 10, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Patent number: 12328256
    Abstract: Techniques for supporting overlapping network addresses universally are disclosed. A system, process, and/or computer program product for supporting overlapping network addresses universally includes generating at least two virtual routers for a cloud security service, the at least two virtual routers including a first virtual router and a second virtual router, routing cloud security service packets using the first virtual router, and routing enterprise subscriber packets using the second virtual router.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: June 10, 2025
    Assignee: Palo Alto Networks, Inc.
    Inventors: Jia Chen, Hao Long, Shu Lin
  • Patent number: 12322727
    Abstract: An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tsan Lee, Wei-Cheng Wu, Tsung-Shu Lin
  • Patent number: 12313500
    Abstract: A leakage quick-detection device for drainage pipes comprises an operating rod assembly, a development module and a probe assembly. The development module comprises a receiving shell. A development board is fixedly connected into the receiving shell. A receiving and transmitting antenna is fixedly connected to the receiving shell and is electrically connected to the development board. The probe assembly comprises a composite platform. Four threaded through-holes are vertically and regularly formed in the composite platform. The change of water flow and water quality can be quickly reflected by ultrasonic data, conductivity data and flow data; compared with a traditional visual detection method, the detection dimensions are richer, the working time of personnel is shortened, more water flow information can be obtained, the labor intensity is reduced, and the troubleshooting accuracy is improved.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: May 27, 2025
    Assignee: SOUTH CHINA INSTITUTE OF ENVIRONMENTAL SCIENCE, MEE (ECOLOGICAL AND ENVIRONMENTAL EMERGENCY
    Inventors: Huaiyang Fang, Weijie Li, Jiale Chen, Zhiwei Huang, Shu Lin, Fantang Zeng
  • Publication number: 20250169119
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 22, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Patent number: 12300743
    Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.
    Type: Grant
    Filed: May 16, 2024
    Date of Patent: May 13, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Publication number: 20250122191
    Abstract: Provided are certain BCL-2 inhibitors, pharmaceutical compositions thereof, and methods of use thereof.
    Type: Application
    Filed: November 10, 2022
    Publication date: April 17, 2025
    Inventors: Hongbin LIU, Hua XU, Weipeng ZHANG, Rui TAN, Jinhua YU, Yunling WANG, Yangli QI, Yue RONG, Zhuo HUANG, Ling CHEN, Chenglin ZHOU, Lihua JIANG, Shu LIN, Xingdong ZHAO, Weibo WANG
  • Patent number: 12278847
    Abstract: An apparatus, having a server and processor, is configured to receive a first set of security rules applicable to a set of users or a set of files for a first period of time. The first set of security rules are executable in an order of priority. The processor receives an interim security policy that is different from the first set of security rules. The interim security policy is applicable to a subset of the set of users for a second period of time that is less than the first period, or a subset of the set of files for a second period of time that is less than the first period. The processor determines, in the first set of security rules, an insertion point among the order of priority. The processor executes, at the insertion point and in the first set of security rules, the interim security policy.
    Type: Grant
    Filed: October 4, 2024
    Date of Patent: April 15, 2025
    Inventors: Viswesh Ananthakrishnan, Liang Li, Shujun Zhao, Ho Yu Lam, Nidhi Shah, Shu Lin, Huijun Veronica Zhu
  • Publication number: 20250096092
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Application
    Filed: November 28, 2024
    Publication date: March 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng
  • Publication number: 20250087550
    Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
  • Patent number: 12249737
    Abstract: A lithium battery cell includes an upper cover module, a first battery electrode group, a second battery electrode group, and a plurality of first electrode connection straps. The first electrode connection straps are stacked together and have the same width and length. A first end of the first electrode connection straps is welded to a first tab, a second end of the first electrode connection straps is welded to a second tab, and a middle part of the first electrode connection straps is welded to a first electrode terminal. An even number of first bending parts are formed between the middle part and the first end, and an even number of second bending parts are formed between the middle part and the second end, and the first bending parts and the second bending parts are symmetrical to each other. Furthermore, a lithium battery cell manufacturing method is also disclosed therein.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: March 11, 2025
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Cheng-Huang Chen, Yi-Hsiang Chan, Shu-Lin Chen, Wei-En Hsu
  • Publication number: 20250069980
    Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Patent number: 12237415
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Publication number: 20250047645
    Abstract: An orchestrator that manages security appliances for an organization determines a sink configured for traffic mirroring and correspondingly configures components for the correlation and secure conveyance. The orchestrator also configures the security appliances. The orchestrator configures the security appliances to copy cryptographic keys (hereinafter “tunnel keys”) and identifiers associated with the keys of secure VPN tunnels established by the security appliances to a repository of the cloud-service provider. The orchestrator configures a virtual machine associated with the mirroring sink with correlation logic. The virtual machine correlates sets of packets aggregated across different mirroring streams and tunnel keys with the associated identifiers. Correlating the sets of packets and the tunnel keys allows an organization to efficiently access the content of the encrypted packets or facilitates secure conveyance.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Tushar Vyankatesh Nargunde, Zhanglin He, Tripti Agarwal, Shu Lin, Jose Carlos Sagrero Dominguez
  • Publication number: 20250046961
    Abstract: A lithium battery cell includes an upper cover module, a first battery electrode group, a second battery electrode group, and a plurality of first electrode connection straps. The first electrode connection straps are stacked together. A first end of the first electrode connection straps is welded to a first tab, a second end of the first electrode connection straps is welded to a second tab, and a middle part of the first electrode connection straps is welded to a first electrode terminal. An even number of first bending parts are formed between the middle part and the first end, and an even number of second bending parts are formed between the middle part and the second end, and the first bending parts and the second bending parts are symmetrical to each other. A lithium battery cell manufacturing method is also disclosed therein.
    Type: Application
    Filed: October 25, 2024
    Publication date: February 6, 2025
    Inventors: Cheng-Huang CHEN, Yi-Hsiang CHAN, Shu-Lin CHEN, Wei-En HSU
  • Publication number: 20250038971
    Abstract: While organizations can employ IPsec based VPNs to securely connect different sites (e.g., branch sites, data centers, and/or virtual private clouds), the security can disrupt network performance by obfuscating information used for load balancing. Disclosed is technology that employs minimal decryption in a secure manner to load balance multiple network traffic flows within a secure connection (“tunnel”) across security appliances that effectively operate as alternative endpoints for the tunnel. The security appliances within a load balancing pool are configured/programmed to share tunnel keys with each other after tunnel establishment and with the load balancer. The load balancer uses the tunnel keys to minimally decrypt in a lookaside memory encrypted packets to ascertain N-tuples. The load balancer then uses the N-tuples to load balance the flows within a tunnel across the security appliances.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Inventors: Fang Lu, Peng Chen, Shu Lin
  • Publication number: 20250022825
    Abstract: In an embodiment, a method includes: forming active devices over a semiconductor substrate; forming an interconnect structure over the active devices, the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate, the seal ring being electrically insulated from the active devices; forming a first passivation layer over the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and over the interconnect structure, the first metal pad having a bowl shape, the second metal pad having a step shape; and depositing a second passivation layer over the first metal pad and the second metal pad.
    Type: Application
    Filed: November 15, 2023
    Publication date: January 16, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Hong-Yu Guo, Tsung-Shu Lin, Hsin-Yu Pan
  • Publication number: 20250022763
    Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Hong-Yu Guo, Tsung-Shu Lin