Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

Abstract: Provided are certain BTK inhibitors, pharmaceutical compositions thereof, and methods of use thereof.

Abstract: An oral drug tablet manufacturing device and a manufacturing method thereof comprise a tablet manufacturing area, a micro-control unit, and a collecting area. The tablet manufacturing area comprises a tablet spraying device having a roller and a piezoelectric nozzle, a medicine powder filling container is communicated to the piezoelectric nozzle, the medicine powder filling container contains a plurality of medicine powders, the medicine powders are sprayed and printed through the piezoelectric nozzle, and then the medicine powders are pressed and flattened through the roller to cause the medicine powders to form a drug tablet. The micro-control unit is disposed in the piezoelectric nozzle, the micro-control unit has a storage module and an execution control module. The storage module stores a tablet spray information, the execution control module controls the tablet spraying device through the tablet spray information, and the collecting area is used to collect the drug tablet.

Abstract: Provided are certain CDK2/4/6 inhibitors, pharmaceutical compositions thereof, and methods of use thereof.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: Techniques for providing localization at scale for a cloud-based security service are disclosed. In some embodiments, a system/method/computer program product for providing localization at scale for a cloud-based security service includes receiving a connection request at a network gateway of a cloud-based security service; performing a source Network Address Translation (NAT) from a registered set of public IP addresses associated with a tenant; and providing secure access to a Software as a Service (SaaS) using the cloud-based security service.

Abstract: A package structure includes a substrate, a semiconductor device and an adhesive layer. The semiconductor device is disposed on the substrate, wherein an angle ? is formed between one sidewall of the semiconductor device and one of sides of the substrate, 0°<?<90°. The adhesive layer surrounds the semiconductor device on the substrate and at least continuously disposed at two of the sides of the substrate, wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.

Abstract: A first UE receives a first Session Initiation Protocol (SIP) INVITE message requesting the first UE to place the RTT call on hold, during an ongoing Real-Time Text (RTT) call with a second UE. In response to the first SIP INVITE message, the first UE sends a first SIP 200 OK message to the second UE, and the first SIP 200 OK message indicates that the first UE is not allowed to send and receive media data. After sending the first SIP 200 OK message, the first UE receives a second SIP INVITE message requesting the first UE to resume the RTT call. In response to the second SIP INVITE message, the first UE sends a third SIP INVITE message to the second UE, and the third SIP INVITE message indicates that the first UE is allowed to send and receive media data.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

Abstract: A semiconductor package includes a first heat dissipation plate, a second heat dissipation plate, a plurality of heat generating assemblies, and a plurality of fixture components. The first heat dissipation plate has a first upper surface and a first lower surface. The first heat dissipation plate includes first through holes extended from the first upper surface to the first lower surface. The second heat dissipation plate has a second upper surface and a second lower surface. The second heat dissipation plate includes second through holes extended from the second upper surface to the second lower surface. The heat generating assemblies are disposed between the first heat dissipation plate and the second heat dissipation plate. The fixture components include fix screws and nuts. The fix screws penetrate through the first heat dissipation plate and the second heat dissipation plate along the first through holes and the second through holes.

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

Abstract: A semiconductor package includes a substrate, a package structure, and a lid structure. The package structure is disposed on the substrate. The lid structure is disposed over substrate, wherein the lid structure includes a main body covering and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: A User Equipment (UE) including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from a mobile communication network. The controller determines whether the mobile communication network supports IMS services. The controller establishes a Packet Data Network (PDN) connection or a Protocol Data Unit (PDU) session with the mobile communication network for the IMS services via the wireless transceiver in response to the mobile communication network supporting the IMS services. The controller sends application data on the PDN connection or PDU session via the wireless transceiver.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

Abstract: Techniques for providing localization at scale for a cloud-based security service are disclosed. In some embodiments, a system/method/computer program product for providing localization at scale for a cloud-based security service includes receiving a connection request at a network gateway of a cloud-based security service; performing a source Network Address Translation (NAT) from a registered set of public IP addresses associated with a tenant; and providing secure access to a Software as a Service (SaaS) using the cloud-based security service.