Patents by Inventor Shu Lin

Shu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363611
    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Publication number: 20240363486
    Abstract: In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Yuan Sheng Chiu, Chih-Kai Cheng, Tsung-Shu Lin
  • Patent number: 12131757
    Abstract: A storage drive assembly is provided. The storage drive assembly includes a storage drive sized and shaped for insertion into a slot within a chassis, a latching mechanism coupled to a first end of the storage drive, the latching mechanism including an actuation component actuable to transition the latching mechanism from a locked state in which the latching mechanism restricts displacement of the storage drive relative to the chassis to an unlocked state in which the latching mechanism enables displacement of the storage drive assembly relative to the chassis, and a drive secure cover plate adapted to removably mate with the latching mechanism in the locked state, the mated drive secure cover plate preventing physical access to the actuation component.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: October 29, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Wu-Shu Lin, Fredrick Anthony Constantino, Kevin Jay Langston, Chia-Ching Huang
  • Patent number: 12113610
    Abstract: The present disclosure relates to the field of communication technologies and in particular to a user-distinguished finite-field resource construction method and a finite-field multiple access system. In order to solve the problem of the limitation of the multiple access resource in the current communication field, the present disclosure employs a user-distinguished finite-field resource construction method to construct a basic-field resource and/or extension-field resource, i.e. finite-field resource. During the use of the finite-field resource, each user sending a binary sequence is assigned one codebook marking symbols that 0 and 1 are respectively mapped into a finite field. The transmitter sends a corresponding finite-field symbol sequence. At the receiver, based on the received finite-field symbols, a finite-field symbol sent by each user can be determined uniquely and thus, a binary symbol sent by each user can be decoded. The present disclosure is applied to the finite-field multiple access system.
    Type: Grant
    Filed: March 21, 2024
    Date of Patent: October 8, 2024
    Assignee: HARBIN INSTITUTE OF TECHNOLOGY
    Inventors: Qiyue Yu, Jiangxuan Li, Shu Lin
  • Publication number: 20240328477
    Abstract: The present invention relates to a shock absorber structure with variable damping, comprising an outer tube, a piston, a shaft, a plurality of spring sets, a cushioning piston cover set, an inlet regulating bolt, and a damping regulating bolt, wherein the outer tube is filled with damping oil. The shaft drives the piston by moving to the upper dead center to produce a primary damping of cushioning, and the cushioning piston cover set and the inlet regulating bolt produce a secondary damping of cushioning to achieve the effect of variable damping. When the shaft reaches the lower dead center, the spring set rebounds and pushes the cushioning piston cover set and the piston for displacement to achieve the cushioning state with variable damping and improve the overall shock absorption and cushioning effect.
    Type: Application
    Filed: July 26, 2023
    Publication date: October 3, 2024
    Inventor: Shu-Lin Kuo
  • Patent number: 12107829
    Abstract: Techniques for providing localization at scale for a cloud-based security service are disclosed. In some embodiments, a system/method/computer program product for providing localization at scale for a cloud-based security service includes receiving a connection request at a network gateway of a cloud-based security service; performing a source Network Address Translation (NAT) from a registered set of public IP addresses associated with a tenant; and providing secure access to a Software as a Service (SaaS) using the cloud-based security service.
    Type: Grant
    Filed: December 6, 2023
    Date of Patent: October 1, 2024
    Assignee: Palo Alto Networks, Inc.
    Inventors: Thomas Arthur Warburton, Shu Lin, Devendra Raut, Jialiang Li, Hao Long
  • Publication number: 20240322931
    Abstract: The present disclosure relates to the field of communication technologies and in particular to a user-distinguished finite-field resource construction method and a finite-field multiple access system. In order to solve the problem of the limitation of the multiple access resource in the current communication field, the present disclosure employs a user-distinguished finite-field resource construction method to construct a basic-field resource and/or extension-field resource, i.e. finite-field resource. During the use of the finite-field resource, each user sending a binary sequence is assigned one codebook marking symbols that 0 and 1 are respectively mapped into a finite field. The transmitter sends a corresponding finite-field symbol sequence. At the receiver, based on the received finite-field symbols, a finite-field symbol sent by each user can be determined uniquely and thus, a binary symbol sent by each user can be decoded. The present disclosure is applied to the finite-field multiple access system.
    Type: Application
    Filed: March 21, 2024
    Publication date: September 26, 2024
    Inventors: Qiyue YU, Jiangxuan LI, Shu LIN
  • Publication number: 20240312557
    Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.
    Type: Application
    Filed: February 16, 2024
    Publication date: September 19, 2024
    Applicant: MEDIATEK INC.
    Inventors: Che-Wei Chou, Ya-Ting Yang, Shu-Lin Lai, Chi-Kai Hsieh, Yi-Ping Kuo, Chi-Hao Hong, Jia-Jing Chen, Yi-Te Chiu, Jiann-Tseng Huang
  • Patent number: 12094836
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Hsuan-Ning Shih, Hsien-Pin Hu, Tsung-Shu Lin, Tsung-Yu Chen, Wen-Hsin Wei
  • Publication number: 20240304705
    Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.
    Type: Application
    Filed: May 16, 2024
    Publication date: September 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Patent number: 12080623
    Abstract: In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Yuan Sheng Chiu, Chih-Kai Cheng, Tsung-Shu Lin
  • Patent number: 12074154
    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Publication number: 20240282659
    Abstract: A semiconductor package includes a first heat dissipation plate, a second heat dissipation plate, a plurality of heat generating assemblies, and a plurality of fixture components. The first heat dissipation plate has a first upper surface and a first lower surface. The first heat dissipation plate includes first through holes extended from the first upper surface to the first lower surface. The second heat dissipation plate has a second upper surface and a second lower surface. The second heat dissipation plate includes second through holes extended from the second upper surface to the second lower surface. The heat generating assemblies are disposed between the first heat dissipation plate and the second heat dissipation plate. The fixture components include fix screws and nuts. The fix screws penetrate through the first heat dissipation plate and the second heat dissipation plate along the first through holes and the second through holes.
    Type: Application
    Filed: April 28, 2024
    Publication date: August 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsiang Lao, Yuan-Sheng Chiu, Hung-Chi Li, Shih-Chang Ku, Tsung-Shu Lin
  • Patent number: 12069025
    Abstract: Techniques for providing a networking and security split architecture are disclosed. In some embodiments, a system, process, and/or computer program product for providing a networking and security split architecture includes receiving a flow at a security service; processing the flow at a network layer of the security service to perform one or more networking functions; and offloading the flow to a security layer of the security service to perform security enforcement based on a policy.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: August 20, 2024
    Assignee: Palo Alto Networks, Inc.
    Inventors: Thomas Arthur Warburton, Hao Long, Shu Lin, Mingfei Peng
  • Publication number: 20240266437
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
  • Publication number: 20240259290
    Abstract: Techniques for deploying symmetric routing are disclosed. A system, process, and/or computer program product for deploying symmetric routing includes routing network traffic from a client over a security access network provider virtual private network (VPN) access to a customer network, and enforcing symmetric routing crossing an autonomous system (AS) based on one or more prepended AS routing numbers in a first routing table for inbound traffic and/or based on one or more weights and one or more local preferences in a second routing table for outbound traffic.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Inventors: Jia Chen, Saurabh Dixit, Anil Saini, Shu Lin, Hao Long
  • Publication number: 20240234340
    Abstract: An integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. The integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. The stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. The stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.
    Type: Application
    Filed: January 9, 2023
    Publication date: July 11, 2024
    Inventors: Yi-Che Chiang, Yuan Sheng Chiu, Hong-Yu Guo, Hsin-Yu Pan, Tsung-Shu Lin
  • Publication number: 20240234223
    Abstract: A manufacturing method of a semiconductor package includes the following steps. A package structure is provided over a substrate. A thermal interface layer is provided over the package structure. A lid structure is provided over the substrate, wherein the lid structure comprises a main body in contact with the package structure through the thermal interface layer and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.
    Type: Application
    Filed: February 6, 2024
    Publication date: July 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Tsung-Yu Chen
  • Publication number: 20240220499
    Abstract: There is provided a method and apparatus for optimizing a database query. Embodiments expand the scope of query optimization to two or more query optimizers. Therefore, a larger class of plan trees can be explored, and a more optimal (for example faster) physical plan may be chosen for execution. The query will continue to be executed by the “original”, “home” or “first” query execution engine, and therefore, a translation or conversion mechanism is be put into place that is able to convert the chosen physical plan into a format that is acceptable to the original optimizer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: HUAWEI CLOUD COMPUTING TECHNOLOGIES CO., LTD.
    Inventors: Arunprasad P. MARATHE, Shu LIN
  • Publication number: 20240222291
    Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
    Type: Application
    Filed: March 12, 2024
    Publication date: July 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin