Patents by Inventor Shu Lin

Shu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230326826
    Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Patent number: 11770359
    Abstract: Described herein are systems, methods, and software to enhance failover operations in a cloud computing environment. In one implementation, a method of operating a first service instance in a cloud computing environment includes obtaining a communication from a computing asset, wherein the communication comprises a first destination address. The method further provides replacing the first destination address with a second destination address in the communication, wherein the second destination address comprises a shared address for failover from a second service instance. After replacing the address, the method determines whether the communication is permitted based on the second destination address, and if permitted, processes the communication in accordance with a service executing on the service instance.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: September 26, 2023
    Assignee: Palo Alto Networks, Inc.
    Inventors: Shu Lin, Patrick Xu, Eswar Rao Sadaram, Hao Long
  • Patent number: 11769833
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: September 26, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Patent number: 11756870
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng
  • Patent number: 11750563
    Abstract: Techniques for providing flow meta data exchanges between network and security functions for a security service are disclosed. In some embodiments, a system/process/computer program product for providing flow meta data exchanges between network and security functions for a security service includes receiving a flow at a network gateway of a security service from a software-defined wide area network (SD-WAN) device; inspecting the flow to determine meta information associated with the flow; and communicating the meta information associated with the flow to the SD-WAN device.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: September 5, 2023
    Assignee: Palo Alto Networks, Inc.
    Inventors: Anand Oswal, Arivu Mani Ramasamy, Bhaskar Bhupalam, Shu Lin
  • Publication number: 20230273925
    Abstract: The present disclosure provides methods and apparatus for calibrating cost estimator for trustworthy DBMS performance. An aspect of the disclosure provides for a method, which includes generating a plurality of plans for potential execution by a DBMS, each of the plurality of plans being configured to generate a same response to a same specified database query. The method further includes generating, for each plan, a set of probability-cost value pairs, each indicative of an estimated upper cost for said plan and a probability that a cost for said plan will be equal to or less than said estimated upper cost, if and when said plan is executed. The method further includes selecting one of the plurality of plans based at least in part on an evaluation of the sets of probability-cost value pairs for the plurality of plans, and causing the DBMS to execute the selected plan.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Applicants: HUAWEI CLOUD COMPUTING TECHNOLOGIES CO., LTD., York University
    Inventors: Yifan LI, Xiaohui YU, Nikolaos KOUDAS, Shu LIN, Calvin SUN, Chong CHEN
  • Publication number: 20230255852
    Abstract: A permeable spraying device for making drug tablets mainly comprises a carrying platform, a spraying equipment, a flattening device and a control equipment, the carrying platform defines a powder dropping area and a flattened spraying area, and a moving device combined with the carrying platform is capable of moving vertically. The spraying equipment is mounted above the carrying platform, and the spraying equipment comprises a powder box, a colloid spraying equipment, a driving device and a placement platform. The placement platform is disposed with a plurality of supplementary colloid carriers. The flattening device is installed on the carrying platform and moves horizontally back and forth in the flattened spraying area. The control equipment is equipped with a storage unit and an execution control unit. A multi-layer drug body structure can be formed by deposition, stacking and bonding.
    Type: Application
    Filed: April 27, 2023
    Publication date: August 17, 2023
    Inventors: KUO-MING HUANG, YEN-SHU LIN, YEN-CHAO YANG, YAO-JEN LIANG
  • Patent number: 11715675
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Patent number: 11714794
    Abstract: The present disclosure provides a method of reading data maintained in a tree data structure, such as B+ tree, using near data processing (NDP) in a cloud native database. According to embodiments, a desired LSN will be used in NDP page reads on the master computing node (e.g. master SQL node). When the master computing node (e.g. master SQL node) reads the regular page, the maximum desired LSN (e.g. the latest page version number) for that regular page will be used. Embodiments use features of the desired LSN and page locking, wherein correct versions of pages can be obtained by using the desired LSN associated with a page, in combination with page locking, and can enable the reading of a consistent tree structure and achieve good read/write concurrency.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: August 1, 2023
    Assignee: HUAWEI CLOUD COMPUTING TECHNOLOGIES CO., LTD.
    Inventors: Shu Lin, Chong Chen
  • Publication number: 20230215774
    Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle ? is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<?<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
  • Publication number: 20230198944
    Abstract: Techniques for providing a networking and security split architecture are disclosed. In some embodiments, a system, process, and/or computer program product for providing a networking and security split architecture includes receiving a flow at a security service; processing the flow at a network layer of the security service to perform one or more networking functions; and offloading the flow to a security layer of the security service to perform security enforcement based on a policy.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Thomas Arthur Warburton, Hao Long, Shu Lin, Mingfei Peng
  • Publication number: 20230198949
    Abstract: Traffic log data generated by cloud firewalls executing in a cloud environment during a time period that indicate classes and corresponding amounts of network traffic detected across sessions as well as usage cost data recorded for the cloud firewalls during the time period are obtained. The traffic log data are preprocessed to generate training data comprising feature vectors indicating the aggregate amount of network traffic detected for each traffic class during a corresponding time interval within the time period and are labeled with the associated usage cost. A machine learning model is trained on the labeled traffic log data to learn the impact each traffic class has on the accumulated usage costs. The trained model generates predicted usage costs based on distributions of detected network traffic across traffic classes that are analyzed to correlate traffic patterns with usage costs to determine the optimal size(s) of cloud firewalls to deploy.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Shangde Zhou, Sheng Meng, Shu Lin
  • Patent number: 11676943
    Abstract: A semiconductor structure includes a first die, second dies coupled to and on the first die, a dielectric layer on the first die and covering each second die, and through dielectric vias (TDVs) coupled to and on the first die. The first die includes a bonding dielectric layer and bonding features embedded in and leveled with the bonding dielectric layer. An array of second dies is arranged in a first region of the first die. Each second die includes a bonding dielectric layer and a bonding feature embedded in and leveled with the bonding dielectric layer. The bonding dielectric layer and the bonding feature of each second die are respectively bonded to those of the first die. The TDVs are laterally covered by the dielectric layer in a second region of the first die which is connected to the first region and arranged along a periphery of the first die.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: June 13, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Huang, Shih-Chang Ku, Tsung-Shu Lin
  • Publication number: 20230174556
    Abstract: Provided are certain PI3K inhibitors, pharmaceutical compositions thereof, and methods of use thereof.
    Type: Application
    Filed: May 14, 2021
    Publication date: June 8, 2023
    Inventors: Zuwen ZHOU, Rui TAN, Hua XU, Qihong LIU, Huajie ZHANG, Bin LIU, Weipeng ZHANG, Zhifu LI, Yanxin LIU, Shu LIN, Xingdong ZHAO, Weibo WANG
  • Publication number: 20230159527
    Abstract: Provided are certain Bcl-2 inhibitors, pharmaceutical compositions thereof, and methods of use thereof.
    Type: Application
    Filed: May 7, 2021
    Publication date: May 25, 2023
    Inventors: Weipeng ZHANG, Hongbin LIU, Rui TAN, Zhifu LI, Yue RONG, Qihong LIU, Zhifang CHEN, Ling CHEN, Hua XU, Zuwen ZHOU, Jinhua YU, Haohan TAN, Bin LIU, Yunling WANG, Lijun YANG, Chengxi HE, Lihua JIANG, Shu LIN, Xingdong ZHAO, Weibo WANG
  • Patent number: 11657066
    Abstract: Methods, processing units, and computer-readable media in a cloud-based database are described. Redo log records are applied to a page at a database replica only when an updated version of the page is requested at the database replica. A log cache may be used by a replica node of the database to track recent redo log records applicable to a given page. The recent redo log records stored in the log cache may be applied to update the page on-demand when an updated version of the page is requested. By applying only the redo log records applicable to pages that are currently being requested, processing resources may be used only to generate pages that are currently required. Methods for registering redo log records into the log cache by the master or replica server are also described.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 23, 2023
    Assignee: HUAWEI CLOUD COMPUTING TECHNOLOGIES CO., LTD.
    Inventors: Chong Chen, Jin Chen, Shu Lin, Chunsheng Sun
  • Publication number: 20230154863
    Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 18, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
  • Patent number: 11652063
    Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin
  • Publication number: 20230144244
    Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
    Type: Application
    Filed: January 12, 2023
    Publication date: May 11, 2023
    Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Publication number: 20230145305
    Abstract: Provided are certain BTK inhibitors, pharmaceutical compositions thereof, and methods of use thereof.
    Type: Application
    Filed: March 10, 2021
    Publication date: May 11, 2023
    Inventors: Chengxi HE, Xianlong WANG, Yue RONG, Rui TAN, Huajie ZHANG, Haohan TAN, Yanxin LIU, Shu LIN, Tongshuang LI, Xingdong ZHAO, Weibo WANG