Patents by Inventor Shu Lin

Shu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11545560
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Patent number: 11527502
    Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
  • Patent number: 11515229
    Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
  • Publication number: 20220369197
    Abstract: A method for enhanced call control using User Equipment (UE)-triggered fallback procedure is provided. A UE starts a guard timer in response to initiating or receiving an Internet Protocol (IP) Multimedia Subsystem (IMS) call in a mobile communication network which utilizes a first Radio Access Technology (RAT). The UE determines whether a condition for call continuation in the mobile communication network is met when the guard timer expires. The UE triggers a fallback from the first RAT to a second RAT in response to the condition for call continuation in the mobile communication network not being met.
    Type: Application
    Filed: April 13, 2022
    Publication date: November 17, 2022
    Inventors: Rohit NAIK, Shu-Lin YANG, Hao-Chen CHOU
  • Publication number: 20220354860
    Abstract: Provided are certain URAT1 inhibitors, pharmaceutical compositions thereof, and methods of use thereof.
    Type: Application
    Filed: June 15, 2020
    Publication date: November 10, 2022
    Inventors: Zuwen ZHOU, Hua XU, Yue RONG, Ling CHEN, Zhifang CHEN, Rui TAN, Lijun YANG, Xianlong WANG, Haohan TAN, Bin LIU, Chenglin ZHOU, Yuwei GAO, Lihua JIANG, Shu LIN, Xingdong ZHAO, Weibo WANG
  • Publication number: 20220359470
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Patent number: 11495686
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: November 8, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Publication number: 20220352060
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng
  • Patent number: 11485707
    Abstract: Provided are compounds of Formula (I), or pharmaceutically acceptable salts thereof, pharmaceutical compositions comprising these compounds thereof, and use of these compounds in preparing drugs for inhibiting ROCK.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 1, 2022
    Assignee: Fochon Pharmaceuticals, Ltd.
    Inventors: Rui Tan, Weipeng Zhang, Yunling Wang, Xingdong Zhao, Tao Cheng, Shu Lin, Weibo Wang
  • Publication number: 20220344305
    Abstract: A semiconductor structure includes a first die, second dies coupled to and on the first die, a dielectric layer on the first die and covering each second die, and through dielectric vias (TDVs) coupled to and on the first die. The first die includes a bonding dielectric layer and bonding features embedded in and leveled with the bonding dielectric layer. An array of second dies is arranged in a first region of the first die. Each second die includes a bonding dielectric layer and a bonding feature embedded in and leveled with the bonding dielectric layer. The bonding dielectric layer and the bonding feature of each second die are respectively bonded to those of the first die. The TDVs are laterally covered by the dielectric layer in a second region of the first die which is connected to the first region and arranged along a periphery of the first die.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Huang, Shih-Chang Ku, Tsung-Shu Lin
  • Publication number: 20220328939
    Abstract: A lithium battery cell includes an upper cover module, a first battery electrode group, a second battery electrode group, and a plurality of first electrode connection straps. The first electrode connection straps are stacked together and have the same width and length. A first end of the first electrode connection straps is welded to a first tab, a second end of the first electrode connection straps is welded to a second tab, and a middle part of the first electrode connection straps is welded to a first electrode terminal. An even number of first bending parts are formed between the middle part and the first end, and an even number of second bending parts are formed between the middle part and the second end, and the first bending parts and the second bending parts are symmetrical to each other. Furthermore, a lithium battery cell manufacturing method is also disclosed therein.
    Type: Application
    Filed: August 25, 2021
    Publication date: October 13, 2022
    Inventors: Cheng-Huang Chen, Yi-Hsiang Chan, Shu-Lin Chen, Wei-En Hsu
  • Patent number: 11469218
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Publication number: 20220318218
    Abstract: The present disclosure provides a method of reading data maintained in a tree data structure, such as B+ tree, using near data processing (NDP) in a cloud native database. According to embodiments, a desired LSN will be used in NDP page reads on the master computing node (e.g. master SQL node). When the master computing node (e.g. master SQL node) reads the regular page, the maximum desired LSN (e.g. the latest page version number) for that regular page will be used. Embodiments use features of the desired LSN and page locking, wherein correct versions of pages can be obtained by using the desired LSN associated with a page, in combination with page locking, and can enable the reading of a consistent tree structure and achieve good read/write concurrency.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Shu LIN, Chong CHEN
  • Patent number: 11459332
    Abstract: Provided are certain TRK inhibitors of formula (I): pharmaceutical compositions thereof, and methods of use thereof.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 4, 2022
    Assignee: Fochon Biosciences, Ltd.
    Inventors: Hongbin Liu, Haohan Tan, Chengxi He, Xianlong Wang, Qihong Liu, Zhifu Li, Zuwen Zhou, Yuwei Gao, Lihua Jiang, Li Linghu, Shu Lin, Xingdong Zhao, Weibo Wang
  • Publication number: 20220235049
    Abstract: Provided are certain BTK inhibitors, pharmaceutical compositions thereof, and methods of use thereof.
    Type: Application
    Filed: June 1, 2020
    Publication date: July 28, 2022
    Inventors: Haohan TAN, Qihong LIU, Bin LIU, Zhifu LI, Xianlong WANG, Zuwen ZHOU, Weipeng ZHANG, Yunling WANG, Chenglin ZHOU, Yuwei GAO, Lihua JIANG, Yanxin LIU, Zongyao ZOU, Shu LIN, Kai YU, Tongshuang LI, Xingdong ZHAO, Weibo WANG
  • Publication number: 20220216123
    Abstract: A package structure includes a substrate, a semiconductor device and an adhesive layer. The semiconductor device is disposed on the substrate, wherein an angle ? is formed between one sidewall of the semiconductor device and one of sides of the substrate, 0°<?<90°. The adhesive layer surrounds the semiconductor device on the substrate and at least continuously disposed at two of the sides of the substrate, wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
  • Publication number: 20220189844
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Application
    Filed: March 8, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Publication number: 20220190160
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.
    Type: Application
    Filed: January 13, 2021
    Publication date: June 16, 2022
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Patent number: 11357220
    Abstract: A dip net provided with lockable hoops capable of being folded leftwards and rightwards comprises a net rod, a hoop mounting base mounted on the net rod, and hoops including a left hoop and a right hoop, wherein mounting plates are arranged on the left side and the right side of the hoop mounting base, and two rotary bases are arranged at the rear end of the left hoop and the rear end of the right hoop and are hinged to the mounting plates through rotary shafts. The left hoop and the right hoop can be folded and are independently connected to the hoop mounting base, so that assembly is convenient; and the size can be reduced for transportation and carrying, so that carrying storage are facilitated.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 14, 2022
    Assignee: HANGZHOU FUFAN INDUSTRY CO., LTD.
    Inventors: Hongjian Xu, Shu Lin, Linrong Hong, Huihai Ge, Xiong Li
  • Publication number: 20220174036
    Abstract: Described herein are systems, methods, and software to enhance failover operations in a cloud computing environment. In one implementation, a method of operating a first service instance in a cloud computing environment includes obtaining a communication from a computing asset, wherein the communication comprises a first destination address. The method further provides replacing the first destination address with a second destination address in the communication, wherein the second destination address comprises a shared address for failover from a second service instance. After replacing the address, the method determines whether the communication is permitted based on the second destination address, and if permitted, processes the communication in accordance with a service executing on the service instance.
    Type: Application
    Filed: February 15, 2022
    Publication date: June 2, 2022
    Inventors: Shu Lin, Patrick Xu, Eswar Rao Sadaram, Hao Long