Abstract: This disclosure describes processes for performing direct memory access (“DMA”) between memory of a host and memory of a smart network interface controller (“SNIC”) connected to a bus of the host. The host runs a host thread in a processor of the host and the SNIC runs a SNIC thread in a processor of the SNIC. The host thread and the SNIC thread facilitate direct access of the SNIC thread to memory locations in the memory of the host. The SNIC thread can fetch data directly from and/or write data directly to the memory locations of the memory of the host over the bus.

Abstract: A compensation method of optical lens includes: providing a lens body with an optical filter, with the lens body having an interference light absorbance portion through which a light beam to pass; providing a first green-confusion absorbance region on the interference light absorbance portion, with the first green-confusion absorbance region having a first blue-green absorbance peak portion; providing a second green-confusion absorbance region on the interference light absorbance portion, with the second green-confusion absorbance region having a second yellow-green absorbance peak portion; and the first blue-green absorbance peak portion absorbing at least one blue-green light while the second yellow-green absorbance peak portion absorbing at least one yellow-green light to provide green chroma enhancement in vision.

Abstract: In some aspects, a package structure includes a substrate and semiconductor devices stacked over the substrate. The semiconductor devices are stacked along a first direction, and at least one of the semiconductor devices comprises one or more pads located on a side surface of the at least one of the semiconductor devices.

Abstract: The present application provides single-domain antibodies targeting CD33 and constructs thereof, including chimeric receptors, immune effector cell engagers and immunoconjugates. Further provided are engineered immune cells (such as T cells) comprising an anti-CD33 chimeric receptor and optionally a second chimeric receptor targeting a second antigen or epitope. Pharmaceutical compositions, kits and methods of treating cancer are also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: Provided herein are antibodies and antigen-binding fragment thereof targeting CLL1, and chimeric antigen receptors (e.g., monovalent CAR, and multivalent CAR including bi-epitope CAR) having one or more anti-CLL1 antigen-binding fragments thereof. Further provided are engineered immune effector cells (e.g., T cells) expressing the chimeric antigen receptors and methods of use thereof.

Abstract: Provided herein are antibodies and antigen-binding fragment thereof targeting CD33, and chimeric antigen receptors (e.g., monovalent CAR, and multivalent CAR including bi-epitope CAR) having one or more anti-CD33 antigen-binding fragments thereof. Further provided are engineered immune effector cells (e.g., T cells) expressing the chimeric antigen receptors and methods of use thereof.

Abstract: A semiconductor fabrication method includes: forming, on a substrate, an epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a fin in the epitaxial stack; forming a sacrificial gate stack on channel regions of the fin; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; performing pre-treatment operations to remove impurities from the at least one sacrificial epitaxial layer; recessing the at least one sacrificial epitaxial layer to form a cavity; forming inner spacer material in the cavity; forming source/drain features; removing the sacrificial gate stack and the at least one sacrificial epitaxial layer in the fins; and forming a metal gate to replace the sacrificial gate stack and the at least one sacrificial epitaxial layer, wherein the inner spacers have sufficient thickness to resist epi damage.

Abstract: Systems, devices, and methods for managing conductive connections for semiconductor devices are provided. In one aspect, a method includes: providing an integrated structure including an array structure in a first region and a conductive connection structure in a second region adjacent to the first region, at least one portion of at least one polysilicon layer being over the conductive connection structure; etching the at least one portion of the at least one polysilicon layer to expose one or more conductive connections in the conductive connection structure; depositing an isolating material over the array structure and the conductive connection structure; and forming conductive vertical interconnect accesses (VIAs) through the isolating material to be in contact with the one or more conductive connections and a conductive layer in the array structure.

Abstract: In one example, a semiconductor device includes a conductive layer, composite structures, conductive posts and first pads. The composite structures may be located on the conductive layer and stacked in a direction perpendicular to the plane in which the conductive layer is located. The composite structure may include a chip, an insulating layer surrounding around the chip, and at least one second pad electrically connected with the chip. The second pad is located on the insulating layer. The second pads of the composite structures are at different locations in the first direction. The first direction is perpendicular to the thickness direction of the composite structures. The conductive posts are located in the insulating layer of the composite structures and each conductive post is connected with one of the second pads and one of the first pads.

Abstract: Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Abstract: The present application provides an antibody, such as a monoclonal antibody (mAb), or an antigen binding fragment thereof, that specifically recognizes PD-L1. Also provided are pharmaceutical compositions, or methods of making and using the antibody or antigen binding fragment thereof.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A manufacturing method for an optical lens device includes: providing an optical substrate layer or an optical laminated substrate layer with a first front side surface and a second rear side surface; processing a heat-setting treatment procedure on a flexible anti-fog film for a predetermined time to form a heat-setting-treated anti-fog film, with the heat-setting-treated anti-fog film corresponding to the second rear side surface of optical substrate layer or optical laminated substrate layer; providing an optical adhesive layer on predetermined area of the second rear side surface of optical substrate layer or optical laminated substrate layer; correspondingly adhering the heat-setting-treated anti-fog film to the second rear side surface of optical substrate layer or optical laminated substrate layer.

Abstract: A manufacturing method for optical lens devices includes: providing a scratch-resistant layer on a first outer surface of a first interchangeable optical layer to form a scratch-resistant interchangeable optical layer; providing an anti-fog layer on a second outer surface of a second interchangeable optical layer to form a second anti-fog interchangeable optical layer; fixing the first interchangeable optical layer and the second anti-fog interchangeable optical layer to form a combined dual optical layer; forming a thermal-isolated space layer between a first inner surface of the first interchangeable optical layer and a second inner surface of the second anti-fog interchangeable optical layer; and utilizing the scratch-resistant layer and the thermal-isolated space layer to prevent thermal-exchanging between the first inner surface of the first interchangeable optical layer and the second inner surface of the second anti-fog interchangeable optical layer.

Abstract: Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Abstract: The present application provides modified immune cells that express TLR receptors. In some embodiments, the modified immune cell further comprises an engineered receptor such as a chimeric antigen receptor (CAR). The present application also provides methods and pharmaceutical compositions for cancer treatment using the modified immune cells described herein.

Abstract: In one set of embodiments, a hypervisor of a host system can receive a packet processing program from a virtual network interface controller (NIC) driver of a virtual machine (VM) running on the hypervisor. The hypervisor can then attach the packet processing program to a first execution point in a physical NIC driver of the hypervisor and to a second execution point in a virtual NIC backend of the hypervisor, where the virtual NIC backend corresponds to a virtual NIC of the VM that originated the packet processing program.

Abstract: A method of fabricating a semiconductor device includes forming, over a substrate, alternating layers of a first semiconductor layer formed of a first semiconductor material and a second semiconductor layer formed of a second semiconductor material, the first semiconductor layers including a first, a second, and a third sub-layers; patterning the alternating layers of the first and the second semiconductor layers to form stacks of the alternating layers; and exposing, under etch conditions, lateral edges of the alternating layers to an etchant to selectively etch recesses in the lateral edges of the first, the second, and the third sub-layers, such that a first lateral depth of the first sub-layer is greater than a second lateral depth of the second sub-layer, and the second lateral depth of the second sub-layer is greater than a third lateral depth of the third sub-layer.

Abstract: Provided are single-domain antibodies targeting CLL1 and constructs thereof, including chimeric receptors, immune effector cell engagers and immunoconjugates. Further provided are engineered immune effector cells (such as T cells) comprising an anti-CLL1 chimeric receptor and optionally a second chimeric receptor targeting a second antigen or epitope. Pharmaceutical compositions, kits and methods of treating cancer are also provided.