Patents by Inventor Shu Yen

Shu Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967582
    Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11943935
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Publication number: 20240093267
    Abstract: A high-throughput automated preprocessing method and a system are applied to a nucleic acid preprocessing apparatus including a control system, a sample transfer area, a nucleic acid extraction area, and a reagent setup area. The control system includes a user interface and guides a user to set up on the user interface. In the sample transfer area, the method includes steps of: a user selecting a sampling tube type, a test protocol and an extraction protocol on the user interface, and the control system performing a sample transfer task. In the nucleic acid extraction area, the method includes steps of: the control system performing a nucleic acid extraction task based on the selected extraction protocol. In the reagent setup area, the method includes steps of: the control system performing a reagent deployment task based on the selected test protocol, and the control system performing a nucleic acid transfer task.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 21, 2024
    Inventors: Wei-Te Hsieh, Chia-Yen Lin, Kuang-An Wang, Keng-Ting Liu, Shu-Hui Huang
  • Patent number: 11934106
    Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Yen Liu, Hui-Fang Kuo, Chian-Ting Huang, Wei-Cyuan Lo, Yung-Feng Cheng, Chung-Yi Chiu
  • Patent number: 11927392
    Abstract: The present disclosure is directed to a wafer drying system and method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the system comprises a wafer drying station configured to dispense a drying gas over one or more wafers to dry the one or more wafers, a valve configured to divert the drying gas to a first portion and a second portion, and an exhaust line configured to exhaust the first portion of the drying gas. The system further comprises a detector configured to receive the second portion of the drying gas and to determine a real time property of the second portion of the drying gas, and a control unit configured to control a feedback operation of the wafer drying station based on the real time property of the second portion of the drying gas.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chun Hsu, Sheng-Wei Wu, Shu-Yen Wang
  • Patent number: 11921434
    Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
  • Patent number: 11923210
    Abstract: In an embodiment, a method includes: immersing a wafer in a bath within a cleaning chamber; removing the wafer out of the bath through a solvent and into a gas within the cleaning chamber; determining a parameter value from the gas; and performing remediation within the cleaning chamber in response to determining that the parameter value is beyond a threshold value.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chun Hsu, Shu-Yen Wang, Chui-Ya Peng
  • Publication number: 20240067746
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 29, 2024
    Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
  • Patent number: 11917837
    Abstract: A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: February 27, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Yung-Han Chiu, Shu-Ming Li, Po-Yen Hsu
  • Patent number: 11915755
    Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
  • Publication number: 20230384689
    Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 30, 2023
    Inventors: Shu-Yen LIU, Hui-Fang KUO, Chian-Ting HUANG, Wei-Cyuan LO, Yung-Feng CHENG, Chung-Yi CHIU
  • Publication number: 20230384030
    Abstract: The present disclosure is directed to a wafer drying system and method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the system comprises a wafer drying station configured to dispense a drying gas over one or more wafers to dry the one or more wafers, a valve configured to divert the drying gas to a first portion and a second portion, and an exhaust line configured to exhaust the first portion of the drying gas. The system further comprises a detector configured to receive the second portion of the drying gas and to determine a real time property of the second portion of the drying gas, and a control unit configured to control a feedback operation of the wafer drying station based on the real time property of the second portion of the drying gas.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chun Hsu, Sheng-Wei Wu, Shu-Yen Wang
  • Patent number: 11770924
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: September 26, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
  • Publication number: 20230299106
    Abstract: A method includes: forming a masking layer on a backside of a substrate, the substrate including pixel regions having photodetectors, transistors being positioned on or in a frontside of the substrate; forming a mask opening in the masking layer by exposing the masking layer to patterned light, the opening including: mask pixel regions that mask the pixel regions; and mask protrusion regions that extend from the mask pixel regions toward a mask crossroad region; forming a substrate opening in the substrate by etching the substrate through the mask opening; and forming an isolation structure in the substrate opening.
    Type: Application
    Filed: June 3, 2022
    Publication date: September 21, 2023
    Inventors: Shu Yen Kung, Jia-Hong Liou, Sheng Chieh Chuang, Chun-Chang Chen, Wei-Lin Chang, Ming Chyi Liu, Tsun-Kai Tsao
  • Patent number: 11742196
    Abstract: In an embodiment, a method includes: receiving a wafer from a first dilution tank; immersing the wafer in a deionization tank, wherein the deionization tank comprises a tank solution that comprises a deionizing solution; determining a metal ion concentration within the tank solution; performing remediation within the deionization tank in response to determining that the metal ion concentration is greater than a threshold value; and moving the wafer to a second dilution tank.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Chao, Shu-Yen Wang
  • Patent number: 11739642
    Abstract: The disclosed embodiment is related to a manufacturing method of a die-formed 3-dimensional plastic impeller of a centrifugal pump and the impeller manufactured thereby, including a mold for twisted blade and a mold for impeller outlet, the mold for twisted blade is configured to form a twisted blade portion of each blade of the impeller, the mold for impeller outlet is configured to form a rear portion of each blade, a hub rim part of the impeller, and a shroud rim part of the impeller so that the hub rim part, the shroud rim part, and the blades are formed in a single piece at the same molding process.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 29, 2023
    Assignee: ASSOMA INC.
    Inventors: Chih-Hsien Shih, Chih-Kuan Shih, Huan-Jan Chien, Shu-Yen Chien, Chin-Cheng Wang, Yuan Hung Lin, Peng-Hsiang Chen
  • Publication number: 20230189498
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
  • Patent number: 11643471
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 9, 2023
    Assignee: GlycoNex Inc.
    Inventors: Tong-Hsuan Chang, Mei-Chun Yang, Liahng-Yirn Liu, Jerry Ting, Shu-Yen Chang, Yen-Ying Chen, Yu-Yu Lin, Shu-Lun Tang
  • Patent number: 11641979
    Abstract: The present invention is concerned with a culinary whisk with an elongate profile defining a longitudinal axis and having a proximal end and a distal end, comprising a handle portion and a utility portion, wherein the utility portion includes a plurality of wire loops, and wherein the wire loop has an asymmetric profile and includes an upper elongate leg portion and a lower foot portion and wherein each wire loop has a web member extending across a wire segment of the lower foot portion.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: May 9, 2023
    Assignee: Dandre Technology Innovation Limited
    Inventors: Shu Yen Wong, Andre Ludwig
  • Patent number: 11631679
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 18, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou