Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

Abstract: A structure improvement of a pump casing with a Polyfluoroalkoxy (PFA) liner which improves manufacturing efficiency, reduces manufacturing cost and improves yield strength, more particular to keep the stiffness of the shaft support and improve yield of the pump casing. The metal pump casing with the PFA liner used for handling corrosive liquids includes a suction casing with PFA liner, and a volute casing with PFA liner for accommodating an impeller. The volute casing also collects and then ejects the liquid through a discharge. The suction casing with the PFA liner and the volute casing with the PFA liner are separately formed as two workpieces by injection molding process and then assembled to form the pump casing so as to reduce the residual stress applied in the PFA liner.

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

Abstract: A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor includes a substrate, two source/drain regions, a gate structure and two salicide layers. The two source/drain regions are partially disposed in the substrate each with a substantially flat top surface higher than a top surface of the substrate, and the two source/drain regions are separated from each other. The two source/drain regions are formed of an epitaxial material. The gate structure is disposed on the substrate between the two source/drain regions. The two salicide layers are disposed on the substantially flat top surfaces of the two source/drain regions, respectively.

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, including a substrate, a gate structure on the substrate and a source/drain region disposed in the substrate at one side of the gate structure and in at least a part of an epitaxial structure, wherein the epitaxial structure includes a first buffer layer, which is an un-doped buffer layer, including a bottom portion disposed on a bottom surface of the epitaxial structure and a sidewall portion disposed on a concave sidewall of the epitaxial structure, an epitaxial layer which is encompassed by the first buffer layer, and a semiconductor layer which is disposed between the first buffer layer and the epitaxial layer. The source/drain region is disposed in the epitaxial structure.

Abstract: The present invention provides a method for forming a semiconductor structure, including: first, a substrate is provided. Next, at least two gate structures are formed on the substrate, each gate structure including two spacers disposed on two sides of the gate structure. Afterwards, a dry etching process is performed to remove parts of the substrate, so as to form a recess in the substrate, and a wet etching process is performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively. In addition, parts of the spacer are also removed through the wet etching process, and each spacer includes a rounding corner disposed on a bottom surface of the spacer.

Abstract: A structure improvement of a pump casing with a Polyfluoroalkoxy (PFA) liner which improves manufacturing efficiency, reduces manufacturing cost and improves yield strength, more particular to keep the stiffness of the shaft support and improve yield of the pump casing. The metal pump casing with the PFA liner used for handling corrosive liquids includes a suction casing with PFA liner, and a volute casing with PFA liner for accommodating an impeller. The volute casing also collects and then ejects the liquid through a discharge. The suction casing with the PFA liner and the volute casing with the PFA liner are separately formed as two workpieces by injection molding process and then assembled to form the pump casing so as to reduce the residual stress applied in the PFA liner.

Abstract: A back-contact solar cell set includes a semiconductor substrate and a contact set. A back-surface of the semiconductor substrate includes a first cell region, a second cell region and a first outer-isolation region which separates said two cell regions. The first outer-isolation region has a first basin region and a first highland region which is higher than the first basin region. The contact set includes a first connecting electrode which covers the first basin region. The first cell region and the second cell region are electrically connected through the first connecting electrode.

Abstract: A power control method of a rack having a plurality of nodes includes the following steps. Power information of each node is received. A total power consumption value of the plurality of nodes according to the power information is calculated. A number of power supply units to be turned on according to the total power consumption value and a maximum supplied power value of a single power supply unit is calculated. At least one primary power supply unit and at least one secondary power supply unit in pairs according to the number of power supply units to be turned on is started. The at least one primary power supply unit provides a duty voltage to the plurality of nodes, and the at least one secondary power supply unit does not provide the duty voltage to the plurality of nodes.

Abstract: A rack server includes multiple power supply backplanes and multiple Fan Controller Boards (FCBs). The power supply backplanes each have a connection unit. The connection unit has multiple connection terminals. One of the connection terminals is coupled to a ground terminal. Positions of the connection terminals of the connection units coupled to the ground terminal are different from each other. The FCBs are coupled to one of the corresponding power supply backplanes respectively. The FCBs each include an addressing circuit and a microcontroller. The addressing circuit is coupled to the connection terminals of the corresponding connection unit, and is used to generate an address signal by detecting and according to a coupling relationship between the connection terminals and the ground terminal. The microcontroller is coupled to the addressing circuit, and is used to receive the address signal, so as to generate corresponding address information.

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract: A fan control device is used for controlling at least one fan. The fan control device comprises a signal modulation unit and a shield unit. The signal modulation unit is used for providing a modulation signal and a duty status signal. The shield unit is coupled to the signal modulation unit and the at least one fan for receiving a standby voltage, the duty status signal, and the modulation signal, as well as for shielding the modulation signal or transmitting the modulation signal to the at least one fan according to the standby voltage and the duty status signal.

Abstract: A power control method for a rack having a plurality of nodes is used for turning on a plurality of main power supplies and standby power supplies in pairs according to an actual number of power supply needed to be turned on. A total power consumption value for the nodes is calculated according to power information of the nodes. A number of power supply needed to be turned on is calculated according to the total power consumption value and a maximum power value for one power supply to obtain the actual number and is smaller than the actual number. When the main power supplies supply operating voltages to the nodes, the standby power supplies do not supply the operating voltages to the nodes. An input source received by the main power supplies is different from that received by the standby power supplies.

Abstract: A power control method of a rack having a plurality of nodes includes the following steps. Power information of each node is received. a total power consumption value of the plurality of nodes according to the power information is calculated. A number of power supply units to be turned on according to the total power consumption value and a maximum supplied power value of a single power supply unit is calculated. At least one primary power supply unit and at least one secondary power supply unit in pairs according to the number of power supply units to be turned on is started. The at least one primary power supply unit provides a duty voltage to the plurality of nodes, and the at least one secondary power supply unit does not provide the duty voltage to the plurality of nodes.

Abstract: A rack server includes multiple power supply backplanes and multiple Fan Controller Boards (FCBs). The power supply backplanes each have a connection unit. The connection unit has multiple connection terminals. One of the connection terminals is coupled to a ground terminal. Positions of the connection terminals of the connection units coupled to the ground terminal are different from each other. The FCBs are coupled to one of the corresponding power supply backplanes respectively. The FCBs each include an addressing circuit and a microcontroller. The addressing circuit is coupled to the connection terminals of the corresponding connection unit, and is used to generate an address signal by detecting and according to a coupling relationship between the connection terminals and the ground terminal. The microcontroller is coupled to the addressing circuit, and is used to receive the address signal, so as to generate corresponding address information.

Abstract: Disclosed herein are antibodies or antigen-binding portions thereof directed against extended Type I chain antigens, in particular extended Type I chain glycosphingolipids, and the uses of the antibodies or antigen-binding portions thereof in the diagnosis, amelioration, treatment or prevention of diseases or disorders in mammals, including humans, resulting from or associated with the improper activity/metabolism or the presence of extended Type I chain antigens, in particular extended Type I chain glycosphingolipids.