Patents by Inventor Shuji Nakamura

Shuji Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8368179
    Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 5, 2013
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: John F. Kaeding, Dong-Seon Lee, Michael Iza, Troy J. Baker, Hitoshi Sato, Benjamin A. Haskell, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8368109
    Abstract: An (Al,Ga,In)N-based light emitting diode (LED), comprising a p-type surface of the LED bonded with a transparent submount material to increase light extraction at the p-type surface, wherein the LED is a substrateless membrane.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: February 5, 2013
    Assignee: The Regents of the University of California
    Inventors: Kenji Iso, Hirokuni Asamizu, Makoto Saito, Hitoshi Sato, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8366830
    Abstract: The present invention discloses a susceptor mounting assembly for holding semiconductor wafers in an MOCVD reactor during growth of epitaxial layers on the wafers, that is particularly adapted for mounting a susceptor in an inverted type reactor chamber. It includes a tower having an upper and lower end with the upper end mounted to the top inside surface of the reactor chamber and a susceptor is arranged at the tower's lower end. Semiconductor wafers are held adjacent to the susceptor such that heat from the susceptor passes into wafers. A second embodiment of a susceptor mounting assembly according to the invention also comprises a tower having an upper and lower end. The tower's upper end is mounted to the top inside surface of the reactor chamber. A susceptor is housed within a cup and the cup is mounted to the tower's lower end.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: February 5, 2013
    Assignee: Cree, Inc.
    Inventors: Shuji Nakamura, Steven DenBaars, Max Batres, Michael Coulter
  • Publication number: 20130022528
    Abstract: A gallium nitride crystal with a polyhedron shape having exposed {10-10} m-planes and an exposed (000-1) N-polar c-plane, wherein a surface area of the exposed (000-1) N-polar c-plane is more than 10 mm2 and a total surface area of the exposed {10-10} m-planes is larger than half of the surface area of (000-1) N-polar c-plane. The GaN bulk crystals were grown by an ammonothermal method with a higher temperature and temperature difference than is used conventionally, using a high-pressure vessel with an upper region and a lower region. The temperature of the lower region is at or above 550° C., the temperature of the upper region is set at or above 500° C., and the temperature difference between the lower and upper regions is maintained at or above 30° C. GaN seed crystals having a longest dimension along the c-axis and exposed large area m-planes are used.
    Type: Application
    Filed: August 23, 2012
    Publication date: January 24, 2013
    Applicant: The Regents of th University of California
    Inventors: Tadao Hashimoto, Shuji Nakamura
  • Patent number: 8357925
    Abstract: A high-power and high-efficiency light emitting device with emission wavelength (?peak) ranging from 280 nm to 360 nm is fabricated. The new device structure uses non-polar or semi-polar AlInN and AlInGaN alloys grown on a non-polar or semi-polar bulk GaN substrate.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: January 22, 2013
    Assignee: The Regents of the University of California
    Inventors: Roy B. Chung, Zhen Chen, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Publication number: 20130019123
    Abstract: Storage system arrangement wherein: when a transmission destination determines that a source-side serial number included in a received packet is the same as a current destination-side serial number in the transmission destination, the transmission destination processes a content of the received packet in accordance with a command included in the received packet; and when the transmission destination determines that the source-side serial number is not the same as the current destination-side serial number, the transmission destination does not process a content of the received packet.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 17, 2013
    Inventors: Makio Mizuno, Shuji Nakamura, Masanori Takada
  • Publication number: 20130015492
    Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.
    Type: Application
    Filed: September 6, 2012
    Publication date: January 17, 2013
    Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Tadao Hashimoto, Hitoshi Sato, Shuji Nakamura
  • Patent number: 8340087
    Abstract: Deadlock is avoided in a grid storage system having superior scalability. Provided is a storage subsystem connected to a host computer for receiving a write or read access from the host computer. This storage subsystem includes a plurality of modules respectively having a storage resource, a switch for connecting the plurality of modules, a controller for controlling the transfer of a packet based on the write or read access from the host computer to a target module among the plurality of modules via the switch, and a memory storing a transfer rule of the packet. The controller controls the transfer of the packet based on the transfer rule.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: December 25, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Nakamura, Akira Fujibayashi, Mutsumi Hosoya, Hideaki Fukuda
  • Patent number: 8334151
    Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: December 18, 2012
    Assignee: The Regents of the University of California
    Inventors: Akihiko Murai, Christina Ye Chen, Daniel B. Thompson, Lee S. McCarthy, Steven P. DenBaars, Shuji Nakamura, Umesh K. Mishra
  • Publication number: 20120313077
    Abstract: High emission power and low efficiency droop semipolar blue light emitting diodes (LEDs).
    Type: Application
    Filed: June 11, 2012
    Publication date: December 13, 2012
    Applicant: The Regents of the University of California
    Inventors: Shuji Nakamura, Steven P. DenBaars, Daniel F. Feezell, Chih-Chien Pan, Yuji Zhao, Shinichi Tanaka
  • Publication number: 20120313076
    Abstract: A light emitting diode structure of (Al,Ga,In)N thin films grown on a gallium nitride (GaN) semipolar substrate by metal organic chemical vapor deposition (MOCVD) that exhibits reduced droop. The device structure includes a quantum well (QW) active region of two or more periods, n-type superlattice layers (n-SLs) located below the QW active region, and p-type superlattice layers (p-SLs) above the QW active region. The present invention also encompasses a method of fabricating such a device.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 13, 2012
    Applicant: The Regents of the University of California
    Inventors: Shuji Nakamura, Steven P. DenBaars, Shinichi Tanaka, Daniel F. Feezell, Yuji Zhao, Chih-Chien Pan
  • Patent number: 8332586
    Abstract: The present invention obtains with high precision, in a storage system, the effect of additional installation or removal of cache memory, that is, the change of the cache hit rate and the performance of the storage system at that time. For achieving this, when executing normal cache control in the operational environment of the storage system, the cache hit rate when the cache memory capacity has changed is also obtained. Furthermore, with reference to the obtained cache hit rate, the peak performance of the storage system is obtained. Furthermore, with reference to the target performance, the cache memory and the number of disks and other resources that are additionally required are obtained.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: December 11, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada
  • Patent number: 8332582
    Abstract: A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: December 11, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Nakamura, Kazuhisa Fujimoto, Akira Fujibayashi
  • Publication number: 20120305937
    Abstract: A semiconductor light-emitting diode, and method of fabricating same, wherein an indium (In)-containing light-emitting layer, as well as subsequent device layers, is deposited on a textured surface. The resulting device is a phosphor-free white light source.
    Type: Application
    Filed: July 16, 2012
    Publication date: December 6, 2012
    Applicant: The Regents of the University of California
    Inventors: Rajat Sharma, Paul Morgan Pattison, John Francis Kaeding, Shuji Nakamura
  • Patent number: 8327032
    Abstract: In order to efficiently utilize processor resources, a storage system according to this invention includes: a protocol processor; a processor; a local router; a first memory; and a disk drive. In the storage system, the protocol processor transmits, upon transmitting a frame to the host computer, information on a transmission state of the frame to the local router, and the local router determines, upon the protocol processor receiving a frame, which of the processors processes the received frame, based on which a subject the received frame requests for an access to, transfers the received frame to the determined processor, determines, upon the protocol processor transmitting a frame, which of the processors processes information on a transmission state of the frame, based on an exchange of the transmitted frame, and transfers the information on the transmission state of the frame to the determined processor.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: December 4, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Nakamura, Akira Fujibayashi, Mutsumi Hosoya
  • Publication number: 20120301634
    Abstract: A gas barrier film having excellent gas barrier properties (e.g., barrier properties against water vapor), a production process of the film, and a device provided with the film are provided. A gas barrier film 10 having high gas barrier properties (e.g., barrier properties against water vapor) is obtainable by forming an anchor layer 12 on at least one side of a base film 11 and forming a barrier layer 13 on the anchor layer, wherein the anchor layer is formed from a cured product of a polymerizable composition containing at least a silicone (meth)acrylate monomer and/or prepolymer, and the barrier layer contains a metal or a metal compound.
    Type: Application
    Filed: January 25, 2011
    Publication date: November 29, 2012
    Inventors: Shuji Nakamura, Yoshikazu Yukami, Kanae Nishimura
  • Patent number: 8321622
    Abstract: The first controller includes a first relay circuit which is a circuit that controls data transfer, and a first processor coupled to the first relay circuit via a first second path. The second controller includes a second relay circuit which is a circuit that controls data transfer, and is coupled to the first relay circuit via the first path, and a second processor coupled to the second relay circuit via a second second path. The first processor is coupled to the second relay circuit not via the first relay circuit but via a first third path, and accesses the second relay circuit via the first third path during an I/O process. The second processor is coupled to the first relay circuit not via the second relay circuit but via a second third path, and accesses the first relay circuit via the second third path during an I/O process.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: November 27, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Nakamura, Emi Nakamura, legal representative, Masahiro Arai, Hideaki Fukuda, Nobuyuki Minowa
  • Publication number: 20120286241
    Abstract: A method for fabricating a III-nitride based semiconductor device, including (a) growing one or more buffer layers on or above a semi-polar or non-polar GaN substrate, wherein the buffer layers are semi-polar or non-polar III-nitride buffer layers; and (b) doping the buffer layers so that a number of crystal defects in III-nitride device layers formed on or above the doped buffer layers is not higher than a number of crystal defects in III-nitride device layers formed on or above one or more undoped buffer layers. The doping can reduce or prevent formation of misfit dislocation lines and additional threading dislocations. The thickness and/or composition of the buffer layers can be such that the buffer layers have a thickness near or greater than their critical thickness for relaxation. In addition, one or more (AlInGaN) or III-nitride device layers can be formed on or above the buffer layers.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 15, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Matthew T. Hardy, Po Shan Hsu, Steven P. DenBaars, James S. SPECK, Shuji Nakamura
  • Patent number: 8312314
    Abstract: A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada
  • Patent number: 8304790
    Abstract: A nitride semiconductor device has a nitride semiconductor layer structure. The structure includes an active layer of a quantum well structure containing an indium-containing nitride semiconductor. A first nitride semiconductor layer having a band gap energy larger than that of the active layer is provided in contact with the active layer. A second nitride semiconductor layer having a band gap energy smaller than that of the first layer is provided over the first layer. Further, a third nitride semiconductor layer having a band gap energy larger than that of the second layer is provided over the second layer.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: November 6, 2012
    Assignee: Nichia Corporation
    Inventors: Shuji Nakamura, Shinichi Nagahama, Naruhito Iwasa