Abstract: A method for forming an inverse-T gate lightly-doped drain (ITLDD) structure for deep sub-micron metal oxide semiconductor (MOS) transistors is disclosed. The present invention includes forming a gate oxide layer on a substrate, and forming stacked-amorphous-silicon layers on the gate oxide layer, where the stacked-amorphous-silicon layers comprise at least two layers. Next, a first dielectric layer is patterned on top of the stacked-amorphous-silicon layer by a photoresist mask, and then a lightly-doped source/drain regions is formed. Thereafter, all of the stacked-amorphous-silicon layers are removed except for the bottom amorphous polysilicon layer. A second dielectric spacer is formed on the sidewalls of the stacked-amorphous-silicon layers and heavily-doped source/drain regions are formed. The bottom layer of the stacked-amorphous-silicon layers is and the gate oxide layer is removed using the spacer as an etch mask.

Abstract: Disclosed is a thin textured tunnel oxide prepared by thermal oxidation of a thin polysilicon film on Si substrate. Due to the rapid diffusion of oxygen through grain boundries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at grain boundries, a textured Si/SiO.sub.2 interface is obtained. The textured Si/SiO.sub.2 interface results in localized high fields and causes a much higher electron injection rate. EEPROM memory cells having the textured Si/SiO.sub.2 exhibit a lower electron trapping rate and a lower interface state generation rate even under high field operation.

Abstract: A process is used to fabricate diodes having an emitter contacted p-n junction. A stack of n.sup.+ -type polysilicon layers are formed one upon the other upon a p-type silicon substrate. In an accordingly fabricated diode, native oxide layers that forms between the n.sup.+ -type polysilicon layer and the p-type substrate would be liable to be broken up, and thicker epitaxial layer would be formed between the same. The p-n junction is with a thickness of 0.05-0.2 .mu.m. As the diode is reverse-biased, for example at -5V, leakage current could be less than 1 n.ANG./cm.sup.2. The reverse-bias breakdown voltage could be larger than -100 V. When forward-biased, the ideality factor of the diode is close to unity.