Abstract: The present invention is a method of manufacturing a high density capacitor for use in semiconductor memories. High etching selectivity between BPSG (borophosphosilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a capacitor with a plurality of horizontal fins. First, a nitride layer is formed on a semiconductor substrate. A stacked layer consists of BPSG and silicon oxide formed on the nitride layer. Then a contact hole is formed in the stacked layer and the nitride layer. A highly selective etching is then used to etch the BPSG sublayers of the stacked layer. Next, a first polysilicon layer is formed in the contact hole and the stacked layer, subsequently, a dielectric layer is formed on the first polysilicon layer. Then, undoped hemispherical-grain silicon (HSG--Si) is formed on the dielectric layer. Next, a portion of the dielectric layer is etched using the HSG--Si layer as a hard mask to expose a portion of the first polysilicon layer.

Abstract: A fork-shaped capacitor of a dynamic random access memory cell is disclosed. This capacitor includes a semiconductor layer (110), and a first dielectric layer (119) formed over the semiconductor layer. The capacitor also includes a first doped region (118) formed on a portion of the first dielectric layer, the first doped region communicating to the semiconductor layer via a hole in the first dielectric layer. At least two second doped regions (122) are formed on the first doped region, each of the doped regions being spaced from each other. Further, at least two third doped regions (126) are formed on the first dielectric layer, each of the third doped regions being spaced from each other, each of the third doped regions being spaced from each of the second doped regions, wherein a portion of each of the third doped regions abuts a sidewall of the first doped region.

Abstract: A method of manufacturing crown shape capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate horizontal fins and a vertical pillar within a crown shaped capacitor. Utilizing the structure as a mold, the present invention can improve the performance of a capacitor by increasing the surface area of the capacitor. First, a composition layer consists of BPSG and silicon oxide formed on a substrate. A highly selective etching is used to etch the BPSG sublayers of the composition layer. Then, a contact hole is formed in the composition layer. Next, a first conductive layer is formed in the contact hole and a conductive spacers are formed on the side wall of the composition layer. Then, the composition layer is removed by BOE solution. Next, a dielectric film and a second conductive layer are respectively formed on the first conductive layer.

Abstract: The method includes forming a gate oxide on a substrate. A stacked-amorphous-silicon (SAS) layer is then formed on the gate oxide. An anti-reflective coating (ARC) layer is formed on the SAS layer. Next, a gate structure is patterned by etching. A silicon oxynitride layer is formed on the substrate, and covered the gate structure. A BSG sidewall spacers are formed on the side walls of the gate structure. A selective epitaxial silicon is grown on the substrate by using ultra high vacuum chemical vapor deposition. Then, an ARC layer is removed to expose the top of the SAS layer. Then, a blanket ion implantation is carried out to implant p type dopant into the SAS layer, the epitaxial silicon and silicon substrate. A SALICIDE layer, a polycide layer are respectively formed on the SAS layer and the epitaxial silicon. Further, the extended source and drain are formed in the step. A thick oxide layer is formed over the substrate and gate structure for isolation. Then, contact holes are generated in the oxide layer.

Abstract: A new method for the manufacturing of a capacitor for a DRAM is disclosed herein. The method for manufacturing a capacitor on a semiconductor wafer including the following steps. Firstly, sequentially forming a first dielectric layer, a first conductive layer, a second dielectric layer and a third dielectric layer formed on the semiconductor wafer. Secondary, the third dielectric layer and a portion of the second dielectric layer are etched. The portion of the second dielectric layer is isotropically etched to form a hemispherical cavity. Next, the second dielectric layer, the first conductive layer and the first dielectric layer is etched sequentially to form a hole in contact with a portion of the semiconductor wafer by using the third dielectric layer as a mask. Subsequently, the third dielectric layer is removed when etching the first dielectric layer. Afterword, a second conductive layer is formed on the second dielectric layer and in the hole.

Abstract: A method to fabricate simultaneously a CMOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The NMOS transistor and PMOS transistor in the portion of the CMOS transistor have both anti-punchthrough and salicide structures and individually with n-LDD and p-LDD structure, respectively. The structure of ESD protective devices is fabricated with self-aligned silicide but without LDD, thus the degradation of ESD protection can be solved. The problems of accumulative aberration in scaled devices can also be alleviated through using blanket ion implantation technology and salicide process to reduce the mask count as shown in the invention.

Abstract: The method of the present invention is a method of forming a gate oxide layer on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a silicon nitride layer is formed over the undoped polysilicon layer. A doped polysilicon layer is formed over the silicon nitride layer. Next, the doped polysilicon layer is patterned to define a gate region. A thermal oxidation is performed on the patterned doped polysilicon gate region to oxidize a portion of the patterned doped polysilicon layer into a thermal oxide film. The thermal oxide film is removed by an etching process. A portion of the first dielectric layer is etched by using the residual doped polysilicon layer as a mask. The undoped polysilicon layer is etched by using the residual doped polysilicon layer and the residual first dielectric layer as a mask. Then, a PSG layer is deposited over the residual nitride layer and the substrate to serve as an ion diffusion source.

Abstract: The present invention includes forming a thin oxide layer and a polysilicon layer on a substrate. A thin silicon nitride layer is then formed on the polysilicon layer. An etching is performed to etch back the silicon nitride layer and the polysilicon layer on a NMOS cell region. Next, a blanket ion implantation is carried out to form lightly doped drain regions. A coding oxide layer is formed on the NMOS cell region. Then, the silicon nitride layer is stripped. A second polysilicon layer is successively deposited over the substrate. The polysilicon layer, the gate oxide layer and the coding oxide layer are patterned to form the gate structures. A second ion implantation is used to implant ions to form LDD regions. Side wall spacers are then formed on the side walls of the gate structures. Next, a third ion implantation is then carried out to dope ions into the substrate thereby forming source and drain regions. A high temperature thermal anneal is performed to activate the dopant.

Abstract: A transistor formed on a semi-conductor substrate, where the transistor includes a gate dielectric layer formed on the semi-conductor substrate. The gate dielectric layer includes a silicon oxynitride sub-layer formed on the semi-conductor substrate and a dielectric sub-layer having relatively high permitivity to an oxide formed on the silicon oxynitride sub-layer. The transistor also includes a barrier layer formed on the gate dielectric layer and a metal gate is formed on the barrier layer. The gate dielectric layer, the barrier layer and the metal gate combine to form a gate structure. Side walls spacers are formed on side walls of the gate structure, and extended source, drain junctions are formed under the side wall spacers in the semi-conductor substrate and adjacent to the gate structure. The transistor also includes source and drain junctions formed in the gate structure next to the extended source, drain junctions.

Abstract: The present invention discloses a method for manufacturing 3-D transistors with high electrostatic discharge (ESD) reliability. Pad oxide layers are on a silicon substrate and a thick field oxide is on the silicon substrate between the pad oxide layer. An oxygen amorphized region is formed in the substrate by using an ion implantation having oxygen ions as dopants and the field oxide as a hard mask. A high-temperature thermal annealing is implemented to convert the oxygen amorphized region into an oxygen implant-induced oxide regions. Then, the pad oxide layers and the field oxide are removed to form a field oxide region on the substrate and silicon islands on the oxygen implant-induced oxide regions. A thin gate oxide is deposited on the surface of the substrate and the silicon islands to seal the silicon islands. Finally, PMOSFETs are formed on the silicon islands and bulk NMOSFET buffers are formed on the field oxide region of the substrate.

Abstract: This invention discloses a novel design for increasing the surface area of a stacked capacitor used in DRAM devices. The upper and lower plates of the capacitor comprises of several concave structures. The concave structures are first produces on an LS-SOG layer using focused ion beam lithography, which is then mapped to the lower plate of the capacitor. A dielectric layer is deposited, after which an upper plate is formed. The concave structures increases the plate area, thereby increasing charge storage capacity.

Abstract: Following with the formation of pad insulator layer and a stacked layer stacked, a gate insulator is formed within the defined gate insulator space. A lightly doped region is doped and the stacked layer and the pad insulator layer is removed. A semiconductor layer is formed and a gate space is defined over the gate insulator through a spacer structure. An anti punchthrough region is formed followed by the formation of a first insulator layer. A gate filling is then formed to fill within the gate space. A portion of the first insulator layer is then removed. A step of doping a plurality of junction ions is applied. A second insulator layer is formed and a thermal process is then proceeded. Finally a metalization process is employed on the semiconductor substrate.

Abstract: A method for fabricating a MOS transistor with an inverse T-shaped air-gap gate structure on a semiconductor substrate is disclosed. The T-shaped air-gap gate structure reduces the parasitic resistance and capacitance; hence device structure operation speed can be improved. The method comprises the following steps: firstly, a gate hollow is defined in the pad oxide/nitride layer. Next an ultra-thin nitrogen rich dielectric as a gate oxide is formed. After that, a thin .alpha.-Si is deposited, then an ion implantation is done to form a punchthrough stopping region. After forming a CVD oxide film, an anisotropic etching is followed to form oxide spacers. An undoped silicon layer then followed to refill the gate hollow region. A CMP processes or a dry etching is done to remove silicon layer until the nitride layer is exposed. Subsequently, the oxide spacers is removed to expose a dual hollow. A LDD implantation is then implanted into the substrate.

Abstract: A method for forming a multiple pillar-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes patterning to form a doped polysilicon layer (118) over a semiconductor substrate (110), wherein at least a portion of the doped polysilicon layer communicates to the substrate. Next, a titanium nitride layer (122) is conformably formed on the doped polysiliocn layer, and a hemispherical grained silicon layer (124) is then formed on the titanium nitride layer, wherein the titanium nitride layer serves as a seed layer for forming the hemispherical grained silicon layer. The present invention also includes etching the titanium nitride layer using the hemispherical grained silicon layer as a mask, and etching portions of the doped polysilicon layer using the titanium nitride layer as an etch mask. Finally, a dielectric layer (136) is formed on the doped polysilicon layer, and a conductive layer (138) is then formed on the dielectric layer.

Abstract: An ultra-short channel MOSFET with the self-aligned silicided contact and the extended ultra-shallow source/drain junction is formed. An extremely short gate region can be defined without being limited with the bottleneck of the existed lithography technology. A good quality gate insulator layer forming from the regrowth of an oxynitride film is provided. A self aligned metal silicide process is performed to form the contacts. A disposable spacer structure is used to remove metal residue and thus the possible path for leakage is eliminated. An ultra shallow region is formed employing the metal silicide as a diffusion source. An extented source/drain region is provided.

Abstract: A CMOS process with inverse-T gate LDD structure uses liquid phase deposition (LPD) processes to achieve a low thermal budget with only six photoresist-masks in a CMOS device. A first photoresist-mask is used to form field oxide regions. A second photoresist-mask is used to implant a P-well. Before the second photoresist-mask is removed, a first LPD oxide layer is used to cover the N-well. The second photoresist-mask is removed, and the first LPD oxide layer is used as a mask for implanting the N-well. The first LPD oxide layer is removed and a polysilicon layer is deposited on the substrate. A third photoresist-mask is used to etch the polysilicon layer to form gate-structures for the NMOS and PMOS devices. A conformal amorphous Si layer is formed on the gate-structures, followed by forming a fourth photoresist-mask over the N-well. A conformal LPD oxide layer is formed on the conformal polysilicon layer over the P-well. N-LDD regions are then implanted.

Abstract: The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a crown shape capacitor with a plurality of horizontal fins. First, a first polysilicon layer is formed on a semiconductor substrate. A composition layer consists of BPSG and silicon oxide formed on a the first polysilicon layer. Then a contact hole is formed in the composition layer and the first polysilicon layer. A highly selective etching is then used to etch the BPSG sublayers of the composition layer. Next, a second polysilicon layer is formed in the contact hole and the composition layer. Then photolithgraphy and etching process is used to etch the second polysilicon layer, composition layer and first polysilicon layer. A third polysilicon layer is subsequently formed on the second polysilicon layer.

Abstract: A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method includes forming a first TEOS layer, a polysilicon layer and a second TEOS layer over the semiconductor substrate. A window is formed through the second TEOS layer to expose a portion of the polysilicon surface. Defined by a first dielectric spacer in the window, the polysilicon layer is etched to expose a portion of the first TEOS layer. The second TEOS layer and the exposed portion of the first TEOS layer are then removed to form a trench extending down to the semiconductor substrate. A polysilicon plug is filled in the trench and a first polysilicon spacer is formed around the first dielectric spacer. A lower electrode including the polysilicon plug, the polysilicon layer and the first polysilicon spacer is therefore formed by removing the first dielectric spacer. Moreover, a dielectric layer and an upper electrode are formed over the lower electrode.

Abstract: The present invention discloses a method of fabricating flash memory cell for use in semiconductor memories. A nitrogen implantation step is added in the process to increase the performance of the device. The nitrogen implanted tunnel oxide exhibits a much higher electron conduction efficiency than the prior art tunnel oxides in both injection polarities. The value of charge-to-breakdown voltage of the nitrogen implanted tunnel oxide is also much larger than the narrow tunnel oxide. In addition, the electron trapping rate of the nitrogen implantation tunnel oxide is very small even under a very large electron fluence stressing (100 C/cm.sup.2).

Abstract: A method for forming an ultra-short channel device with an inverse-T gate lightly-doped drain (ITLDD) structure is disclosed. The method includes forming a silicon layer (14) over a semiconductor substrate (10), and forming a dielectric layer (16) on the silicon layer. Next, a sacrificial region (18) is formed on the dielectric layer to define a gate region. A portion of the sacrificial region is oxidized to form a oxide layer (22) in the sacrificial region and along sidewalls and top surface of the sacrificial region, wherein at least a portion of the sacrificial region is unoxidized. The dielectric layer and a portion of the silicon layer are then removed using the oxide layer as a mask, thereby forming a step in the silicon layer. After removing the oxide layer, the silicon layer is removed using the unoxidized sacrificial region and the dielectric layer as a mask, thereby resulting in an inverse-T structure in the silicon layer.