Abstract: The method of the present invention includes forming a silicon oxynitride layer on a substrate. Then, a dielectric layer with high permitivity is deposited by chemical vapor deposition on the silicon oxynitride layer. Subsequently, a rapid thermal process (RTP) anneal is performed in N.sub.2 O or NO ambient to reduce the dielectric leakage. A multiple conductive layer consisting of TiN/Ti/TiN is then formed on the dielectric layer. Then, the multiple conductive layer, the dielectric layer, and the silicon oxynitride layer are patterned to form gate structure. A plasma immersion is performed to form ultra shallow extended source and drain junctions. Side wall spacers are formed on the side walls of the gate structure. Next, an ion implantation is carried out to dope ions into the substrate. Next, a rapid thermal process (RTP) anneal is performed to form shallow junctions of the source and the drain.

Abstract: A semiconductor processing method for forming self-aligned T-gate Lightly-Doped Drain (LDD) device of recessed channel is presented. The method comprises the steps of covering a substrate with pad oxide, forming a lightly-doped layer by ion implantation, depositing a silicon nitride layer on the surface of the pad oxide, and etching the silicon nitride layer according to a predefined mask pattern to expose the silicon oxide layer and to form a gate region. A polysilicon spacer region is formed on the side-walls of the silicon nitride layer. Anisotropic etch is used to etch the polysilicon spacer region, and at the same time etch the exposed pad oxide and a portion of the substrate to form a T-shaped groove. An amorphous silicon layer is deposited in the T-shaped groove after forming a thin oxide layer, then the amorphous silicon deposited apart from the T-shaped groove region is removed. The silicon nitride layer is removed to form a T-gate.

Abstract: A method of manufacturing porous-Si capacitors for use in semiconductor memories is disclosed herein. The present invention includes a SOG layer as an etching mask to etch a polysilicon layer to form a porous-Si structure. The etching process is performed to etch a portion of the first conductive layer and to etch away the remaining HSG-Si. Next, the residure SOG layer is removed to define a porous-Si bottom storage. Utilizing the porous-Si structure, the present invention can be used to increase the surface area of the capacitor.

Abstract: A method for forming a semiconductor device with a graded lightly-doped drain (LDD) structure is disclosed. The method includes providing a semiconductor substrate (10) having a gate region (14 and 16) thereon, followed by forming a pad layer (18) on the substrate and the gate region. Next, ions are implanted into the substrate, and a spacer (22) is formed on sidewalls of the gate region, wherein the first spacer has a concave surface inwards on a surface of the first spacer. Finally, ions are further implanted into the substrate using the gate region and the spacer as a mask, thereby forming a graded doping profile (20) in the substrate.

Abstract: A stacked layer is formed over a sunstrate. The stacked layer consists of at least three, preferably four, layers with different etching rates under a certain etchant with one another. An etching is used to etch the stacked layer to define a storage node using a photoresist as a mask. Then, a selectively etching is performed to etch the stacked layer. A polysilicon layer is than conformily formed along the surface of the stacked layer. Then, an anisotropically etching is carried out to etch the polysilicon layer. The polysilicon layer on the top of the stacked layer is completely removed to expose the top layer of the stacked layer. Next, the stacked layer is removed to form two stair-like structures. A dielectric layer is deposited along the surface of stair-like structures. Finally, a conductive layer is deposited over the dielectric layer.

Abstract: A method of fabricating a short-channel MOS device on a substrate is provided. First, stacked pad oxide/nitride layers are formed on the substrate. Then a patterned photoresist film is formed on the planned gate region which covers the gate region and its sidewall spacers. A LPD (Liquid Phase Deposition) oxide is selectively deposited on the pad nitride layer by a liquid phase deposition process, except on the pre-formed photoresist film. After removing the photoresist layer nitride spacers leaning against the LPD oxide layer are formed by lithography and etching. The width of the nitride spacers controls the channel length of the MOS device. After forming a gate structure laterally sandwiched by the nitride spacers on the exposed substrate, a two-stage salicide process, which can form shallow junctions and self-aligned contacts on the source and the drain, is performed to complete the MOS device.

Abstract: A method for forming a ragged polysilicon crown-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first dielectric layer (122) on a semiconductor substrate, and then forming a first silicon nitride layer (124) on the first dielectric layer. Next, a portion of the first silicon nitride layer is removed to form a first hole therein. A first polysilicon spacer (126) is then formed on sidewall of the first silicon nitride layer. Portions of the first dielectric layer are etched, therefore exposing a surface of the substrate, and forming a second hole in the first dielectric layer. Subsequently, a second doped polysilicon layer (128) is formed, thereby refilling the second hole. A second silicon nitride layer (130) is then formed, and the second silicon nitride layer and the second doped polysilicon layer are patterned to form a storage node.

Abstract: A method of fabricating a rugged-crown shaped capacitor on a semiconductor substrate is provided. Specifically, the method can be applied for fabricating a storage capacitor of a DRAM cell. A doped polysilicon layer is deposited on the substrate and patterned to retain the portion of the doped polysilicon layer within a planned region of the capacitor. Next, an undoped polysilicon layer is deposited on the doped polysilicon layer and the substrate and etched back as undoped polysilicon spacers. Then the doped layer and the undoped spacers are selectively etched by a hot H.sub.3 PO.sub.4 solution to form a crown-shaped node of the capacitor with a rugged surface. Then the undoped portion of the crown-shaped node of the capacitor is doped and the rugged-crown shaped node forms a conductive plate of the DRAM capacitor, providing a rugged-crown shaped capacitor having a larger area to increase its capacitance.

Abstract: A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method includes forming successively, a TEOS layer, a first dielectric layer and an insulating layer over the semiconductor substrate. Then a window filled with a polysilicon plug through the three layers is formed. The insulating layer is patterned by an HSG-Si layer deposited thereon, thereby forming a polysilicon rod and a plurality of insulating rods. A conducting polysilicon layer is formed over the polysilicon rod and the plurality of insulating rods when the HSG-Si layer is removed. The first dielectric layer and the insulating rods are removed, thereby forming a rake-shaped electrode which includes the polysilicon rod and the conducting polysilicon layer. Moreover, a second dielectric layer and another electrode are formed over the rake-shaped electrode.

Abstract: A method for fabricating a stacked capacitor is disclosed. The method includes forming successively a first dielectric layer, a first polysilicon layer and an insulation layer over a semiconductor substrate. The three layers are patterned to have a window in which a portion of the substrate is exposed. A second polysilicon layer is deposited over the insulation layer and filled in the window. The second polysilicon layer and the insulation layer are patterned to form an island. A dielectric spacer around the island is formed. Moreover, the second polysilicon layer over the insulation layer and the first polysilicon uncovered by the island are removed. The insulation layer in the island is then removed to leave a polysilicon rod surrounded by the dielectric spacer. Polysilicon spacers around the polysilicon rod and the dielectric spacer are formed and the dielectric spacer is removed, thereby forming a lower electrode.

Abstract: A process for forming a shallow trench isolation is disclosed. Initially, a gate oxide layer is formed on a substrate, and a silicon nitride, which defines an active area, is then patterned on the gate oxide layer. Next, hemispherical grain silicon is formed on the silicon nitride, the sidewalls of the silicon nitride, and the exposed gate oxide layer. Portions of the gate oxide layer are removed to form oxide islands using the silicon nitride and the hemispherical grain silicon as mask. Thereafter, portions of the substrate are removed using the oxide islands as mask. Finally, the exposed substrate is thermally oxidized to form the field oxide structure of the present invention.

Abstract: A method of fabricating a MOS device having a gate-side air-gap structure is provided. A nitride spacer for reserving space of the air gap is formed on the substrate adjacent to the gate structure. An amorphous silicon spacer for forming the sidewall spacer and sealing the air gap is formed adjacent to the nitride spacer. The upper portion of the amorphous silicon spacer is heavily doped during the source/drain implantation. After removing the nitride spacer the doped amorphous silicon spacer is oxidized by a wet oxidation process to form a doped oxide spacer. The growing doped oxide spacer will seal the hole for the nitride spacer resulting from the heavily doped upper portion having a higher oxidation rate than that of other portions. Dopants implanted in the amorphous silicon spacer migrate into the substrate and extended ultra-shallow doped regions are formed that reduce the series resistance of the LDD structure.

Abstract: The present invention is a method of manufacturing porous-Si capacitors for use in semiconductor memories. The present invention uses a silicon oxide layer as an etching mask to etch a polysilicon layer to form a porous-Si structure. The etching process is performed to etch a portion of the polysilicon layer and to etch away the remaining HSG-Si. Next, an oxide layer which is in micro grooves is removed to define a porous-Si bottom storage. The present invention can be used to increase the surface area of the capacitor.

Abstract: A method for forming a ring-shape capacitor in a dynamic random access memory is disclosed. The present invention includes forming a first dielectric layer on a substrate. After a silicon nitride layer is formed on the first dielectric layer, a first doped polysilicon layer is formed on the silicon nitride layer, and a second dielectric layer is formed on the first doped polysilicon layer. After removing portions of the second dielectric layer, the first doped polysilicon layer, the silicon nitride layer and the first dielectric layer by a first photoresist layer, a contact hole is formed. A second doped polysilicon layer is formed over the second dielectric layer, and the contact hole is thus filled by the second doped polysilicon layer. Thereafter, portions of the second doped polysilicon layer and the second dielectric layer are removed using a second photoresist layer as a mask, thereby exposing the first doped polysilicon layer.

Abstract: A method for forming a tungsten silicide polycide gate electrode within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the tungsten silicide polycide gate electrode which is formed through the method. Formed upon a semiconductor substrate is a gate oxide layer. Formed upon the gate oxide layer is a first polysilicon layer which is formed through annealing a first amorphous silicon layer. Formed upon the first polysilicon layer is a second polysilicon layer which is formed through annealing a second amorphous silicon layer. Formed upon the second polysilicon layer is a tungsten silicide layer formed through a Chemical Vapor Deposition (CVD) method. The first polysilicon layer and the second polysilicon layer have a crystallite size no greater than about 0.3 microns, and the first polysilicon layer and the second polysilicon layer have a dopant concentration larger than about 1E16 atoms per cubic centimeter.

Abstract: An improved local oxidation of silicon (LOCOS) method using encapsulating polysilicon/silicon nitride spacer is disclosed. The method includes forming a pad oxide layer on a semiconductor substrate and forming a first silicon nitride layer on the pad oxide layer. The pad oxide layer and the first silicon nitride layer are then patterned and etched by a photoresist mask to define an active region. After removing a portion of the pad oxide layer, an undercut between the first silicon nitride layer and the substrate is formed. A silicon oxide layer is thereafter formed on the substrate, and a polysilicon layer is formed to encapsulate the first silicon nitride layer, the pad oxide layer and the silicon oxide layer. Next, a second silicon nitride layer is formed and etched back to form a silicon nitride spacer on the sidewalls of the polysilicon layer.

Abstract: A CMOS device with buried contacts is formed using a polysilicon stack layer and twin-well and liquid phase deposition (LPD) processes. A gate oxide layer and a first polysilicon layer are formed on a substrate. Then the gate oxide and first polysilicon layer are etched to form gate structures. A polysilicon stack layer is formed on the gate structures. The polysilicon stack layer and the first polysilicon layer are anisotropically dry etched, forming first trenches that expose portions of the gate oxide and portions of the substrate defining S/D regions for a NMOSFET. A NMOS lightly doped drain (LDD) with halo doping profile is implanted. A first LPD oxide is selectively formed in the first trenches. Subsequently, a first heavy ion implantation is performed into the polysilicon stack layer for forming the source, drain, gate and buried contacts of the NMOSFET. Trenches are formed in the polysilicon stack layer and first polysilicon layer to define S/D regions and buried contacts for a PMOSFET.

Abstract: An improved local oxidation of silicon (LOCOS) method with recessed silicon substrate and double polysilicon/silicon nitride spacer is disclosed. The present invention includes forming a pad oxide layer on a semiconductor substrate and then forming a first silicon nitride layer on the pad oxide layer. An active region is defined by patterning and etching the pad oxide layer and the first silicon nitride layer using a photoresist mask. Thereafter, a silicon oxide layer and a second silicon nitride layer is formed. Next, a polysilicon layer is deposited over the second silicon nitride layer. The polysilicon layer, the second silicon nitride layer, and the silicon oxide layer are etched back to form a double polysilicon/silicon nitride spacer. Finally, an isolation region in the substrate is formed.

Abstract: The present invention is a method of manufacturing crown shape capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a tooth like structure within a crown shaped capacitor. Utilizing the structure as a mold, the present invention can form the crown shape structure with horizontal fins to increase the surface area of the capacitor.

Abstract: A method of fabricating a capacitor having multiple pillars is presented. The invention uses an oxidized hemispherical grain silicon (HSG-Si) layer as a masking layer, in a series of masking steps, to form pillarets on a storage electrode. The method begins by forming a storage electrode having a connection to an active area on the substrate. Next, a cap insulation layer and a cap polysilicon layer are formed over the storage electrode. The cap polysilicon layer has grains and has grain boundaries between the grains. The cap polysilicon layer is oxidized thus forming a thicker oxide layer at the grain boundaries. The oxide layer is dry etched exposing the cap polysilicon layer and leaves a grain boundary oxide covering the grain boundaries. Next, the exposed cap polysilicon layer is etched using the grain boundary oxide as a mask forming a plurality of cap polysilicon layer pillarets. The grain boundary oxide is then removed.