Abstract: The present invention includes forming a pad oxide layer on a substrate. A silicon nitride layer is deposited on the pad oxide. Then, an etching process is used to etch the silicon nitride layer, pad oxide. Subsequently, a silicon oxynitride layer is formed on the substrate. An undoped polysilicon layer is deposited on the silicon nitride layer and silicon oxynitride layer. Subsequently, polysilicon side wall spacers are formed. Then, the silicon nitride layer is removed to expose the pad oxide. Then, a blanket ion implantation is carried out to implant dopant into the side wall spacers, and through the pad oxide or the silicon oxynitride layer into the substrate. An oxide layer is deposited on the polysilicon side wall spacers. Then, a chemical mechanical polishing (CMP) is performed for planarization. A further silicon oxynitride layer is grown at the top of the polysilicon side wall spacers. Next, a doped polysilicon layer is formed on the oxide, polysilicon side wall spacers as word line.

Abstract: The memory cell in the present invention is formed in a semiconductor substrate with isolations formed upon to separate cells. The cell has an oxide layer between the isolations. The oxide layer includes a pad oxide member, two tunnel oxide members, and two insulating oxide members. The two insulating oxide members are separated from both sides of the pad oxide member by the two tunnel oxide members. The two tunnel oxide members are thinner than the pad oxide member and the two insulating oxide members. The memory cell has a doped junction region in the semiconductor substrate under the two insulating oxide members and the two tunnel oxide members. The cell also has a first conductive layer over the oxide layer and a dielectric layer over the first conductive layer. A second conductive layer is located over the dielectric layer. In addition, the memory cell can further include an undoped hemispherical grain (HSG) silicon film between the first conductive layer and the dielectric layer.

Abstract: The present invention proposes a method for fabricating a high-density shallow trench contactless nonvolatile memory. First, a stacked pad oxide/silicon nitride layer is deposited on the substrate and the buried bit line region is defined by a photoresist. An anisotropic etching follows to etch the silicon layer and then the n+ impurity ions are implanted to form the source and drain. After stripping the photoresist, a high temperature steam oxidation process is used to grow a thick field oxide, and the doped ions are active and driven in to form the buried bit lines simultaneously. The silicon nitride layer and the pad oxide layer are then removed, and the silicon substrate is recessed by using the field oxide as an etching mask. After rounding the trench corners by using thermal oxidation and etching back processes, a thin silicon oxy-nitride film is regrown. An in-situ doped polysilicon film is deposited to refill the trench region and then etch back by using a CMP process to form the floating gates.

Abstract: A double-crown shaped capacitor of a dynamic random access memory cell is disclosed. The capacitor includes a first crown-shaped conductive region formed over a semiconductor substrate, wherein the first crown-shaped conductive region communicates to the semiconductor substrate via a hole. The capacitor also includes a second crown-shaped conductive region formed over the semiconductor substrate, wherein the inner sidewall of the second crown-shaped conductive region abuts on the outer sidewall of said first crown-shaped conductive region. Finally, the capacitor includes a dielectric layer covering the first crown-shaped conductive region and the second crown-shaped conductive region, and includes a conductive layer (138) formed on the dielectric layer.

Abstract: A double-crown shaped capacitor of a dynamic random access memory cell is disclosed. The capacitor includes a first crown-shaped doped polysiliocn region (118) formed over a semiconductor substrate (110), wherein the first crown-shaped doped polysiliocn region communicates to the semiconductor substrate. The capacitor also includes a second crown-shaped doped polysilicon region (128) formed over the semiconductor substrate, wherein the inner sidewall of the second crown-shaped doped polysilicon region abuts on the outer sidewall of aid first crown-shaped doped polysiliocn region. Finally, the capacitor includes a dielectric layer (136) covering the first crown-shaped doped polysiliocn region and the second crown-shaped doped polysilicon region, and includes a conductive layer (138) formed on the dielectric layer.

Abstract: The method of forming buried contacts on a semiconductor substrate is as follows. At first, a gate insulator layer is formed over the substrate. A first silicon layer is then formed over. A buried contact opening is defined through the first silicon layer and the gate insulator layer extending down to the substrate. The substrate is then doped for forming a buried contact region. Next, a second silicon layer and a masking layer is formed. A shielding opening is then defined through the masking layer and the second silicon layer to a portion of the buried contact region. At the same time, an upper gate electrode and an interconnect are defined by removing a portion of the second silicon layer. A shielding layer is formed in the shielding opening over the buried contact region. A lower gate electrode is then defined by removing a portion of the first silicon layer.

Abstract: First, a field oxide region, a pad oxide layer and a first nitride layer are formed on a silicon substrate, respectively. Then, a portion of the first nitride layer is removed. A first oxide layer and a nitride spacer are formed on the substrate, respectively. Portions of the first oxide layer and the pad oxide layer are removed to form a first region of the first oxide layer and a second region of the first oxide layer. Then, an ion implantation is performed to form a punch-through stopping region. Next, a second oxide layer and an amorphous-Si layer are formed on the substrate, respectively.Portions of the a-Si layer are etched back. Next, the first nitride layer and the nitride spacer are removed. An ion implantation is performed to form a source, a drain and a doped region at the bottom of the second region of the first oxide layer. Then, a Rapid Thermal Process is used to drive dopant diffusion to form an extended source/drain junction.

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. A polysilicon layer is than formed, followed by chemical mechanical polishing the layer. A conductive layer is formed on the polysilicon layers. Subsequently, a silicon nitride layer deposited by jet vapor deposition (JVD) is formed on the conductive layer. A high k dielectric layer is next formed on the JVD nitride.

Abstract: The method of the present invention is a method of including forming an oxide layer on the substrate. A nitride layer is subsequently formed on the oxide layer. A photoresist layer is formed on the nitride layer to define isolation regions that uncovered by the photoresist layer. A liquid phase deposition oxide is deposited on the isolation regions. Then the photoresist layer is removed. After removing the photoresist layer, an oxygen ion implantation is performed through the oxide layer and the nitride layer into the substrate by using the liquid phase deposition oxide layer as implant mask to form relative high oxygen ion contained regions in the substrate. After the ion implantation is done, the liquid phase deposition oxide layer is removed. An annealing process is carried out to form isolation regions in the substrate and recover implant-induced damage.

Abstract: The present invention discloses a method to fabricate the non-silicide region for an ESD protective devices in a substrate. Firstly, a substrate is provided and it has field oxide regions to define an electrostatic discharge (ESD) region, a PMOS region and an NMOS region. A gate and a gate oxide for the NMOS region and the PMOS region are define. An N-type and a P-type ion implantation are respectively performed to form a lightly doped drain (LDD) for said NMOS region and said PMOS region. A P-type and an N-type implantation is implemented to form source/drain regions for the NMOS device and the PMOS device, respectively. Afterwards, a silicon oxide layer is defined to form spacers for the polysilicon layer and the gates for the NMOS region and the PMOS region. A self-aligned silicide process is performed to form a silicide layer on the gate and the source/drain regions for the PMOS device and the NMOS device.

Abstract: The present invention includes a gate oxide. A gate is formed on the gate oxide. Undercut portions, formed under the gate. The substrate has recessed portions are adjacent to the gate. A silicon oxynitride layer is formed on the side walls of the gate and refilled into the undercut portions to be used as a portion of the gate oxide. Side wall spacers are formed on the side walls of the gate. A polycide layer is formed at the top of the gate to reduce the electrical resistance. Source and drain regions are formed in the recessed portions of the substrate. Lightly doped drain (LDD) structures are formed in the substrate adjacent to the gate and under the gate oxide. Extended source and drain are formed between the source and drain and the LDD structure to suppress the short channel effect. Self-aligned silicide (SALICIDE) layers are formed at top of the source and drain.

Abstract: The present invention discloses a method of forming CMOS transistors with planar shallow trench isolations. Before a twin well being formed, a pad oxide film and a nitride film are sequentially deposited on a silicon substrate. When a photoresist film is patterned to define active regions, the silicon substrate is recessed by using the patterned photoresist film as a mask. A liquid-phase-deposition oxide (LPD) film is then grown on the recess structure for shallow trench isolations. Next, a high temperature annealing procedure is performed to densify the LPD oxide film. Finally, when the pad oxide and the nitride films are removed, processes for fabricating CMOS transistors can be continued on the silicon substrate.

Abstract: The method of forming a MOS transistor in a semiconductor substrate with the self-aligned silicide contact for ESD protection includes the following steps. At first, an isolation region is formed to separate an ESD protective region and a functional region. A gate insulator layer and a polysilicon layer are formed. The polysilicon layer is then patterned to form a gate structure. The substrate is doped to form a lightly doped region and the ESD protective region is then doped to have a junction region. A covering layer is then formed over the ESD protective region and a first dielectric layer is formed. A portion of the first dielectric layer is removed to form a spacer structure. A silicidation process is performed to form a metal silicide layer and the metal silicide layer is then doped. A second dielectric layer is formed and a thermal process is then performed to form a junction region in the functional region.

Abstract: The present invention includes forming an oxide layer, nitride on a substrate. An ion implantation is performed. A LPD-oxide is formed on P well. Subsequently, an ion implantation to dope phosphorus into the substrate to form N well. Then, the LPD-oxide is removed. The oxide layer and the silicon nitride layer are respectively removed. Subsequently, a thin gate oxide is regrown on the surface of the substrate. A polysilicon layers, a second nitride are deposited on the oxide layer. Polysilicon gates are patterned. An ion implantation is carried out to implant arsenic into the P well. A thin LPD-oxide is forged along the surface of the gate, the substrate on the P well. A thermal anneal process is used to condense the LPD-oxide. Simultaneously, an ultra thin silicon oxynitride layer is formed on the surface of N well. Next, BSG side wall spacers are formed on the side walls of the gates. The silicon nitride layer is removed.

Abstract: The present invention proposes a method for fabricating shallow trench regions for isolation. An oxide hard mask is utilized for the silicon etching. A thick thermal oxide film is created at and near the trench corners to prevent the gate wrap-around and corner parasitic leakage. Forming trench regions on a semiconductor substrate by using a thick pad oxide layer as an etching hard mask. A thermal oxide film is grown to recover the etching damages. An undoped LPCVD amorphous silicon film is then deposited on entire surface of the semiconductor substrate. A high temperature/pressure oxidation process follows to convert the undoped amorphous silicon film into thermal oxide. A thick CVD oxide layer is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.

Abstract: A silicon oxide layer is formed on the wafer to act as a pad layer. A silicon nitride layer is then formed on the silicon oxide layer to have a thickness approximate 1500-2000 angstroms. At least one trench is then created in the wafer. Then, an ion implantation process is performed with at least one titled angle to dope ions into the surface of the trenches. A LPD-oxide is selectively deposited in the trench. Then, a polysilicon layer is formed on the LPD-oxide and on the surface of the silicon nitride layer. Next, the polysilicon layer is etched to generate polysilicon side-wall spacers. The LPD-oxide is etched using the polysilicon side-wall spacers and the silicon nitride layer as an etching mask. The polysilicon side-wall spacers are then removed. A first conductive layer is formed on the silicon nitride layer, and refilled into the first trenches. The first conductive layer is then etched to at least to expose the LPD-oxide. The LPD-oxide is removed.

Abstract: A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer (12) on a semiconductor substrate (10), and forming an oxidation masking layer (14) on the pad layer, wherein the pad layer relives stress from the oxidation masking layer. Next, the oxidation masking layer and the pad layer are patterned and etched to expose a portion of the substrate. After laterally removing the pad layer to form at least one undercut under the oxidation masking layer, a doped layer (16) is conformably formed on the oxidation masking layer, the pad layer, and the substrate, thereby refilling the undercut with the doped layer. Finally, the doped layer is anisotropically etched to form spacers (16A) on sidewalls of the oxidation masking layer and the pad layer, and the substrate is then thermally oxidized to form the isolation region (18) in the substrate, wherein doping atoms in the doped layer will diffuse into the substrate.

Abstract: An ultra-short channel device with an inverse-T gate lightly-doped drain (ITLDD) structure is disclosed. The present invention includes a semiconductor substrate, which includes a top surface; a source region formed in the semiconductor substrate; and a drain region formed in the semiconductor substrate spaced from the source region by a channel region. Further, the present invention also includes an inverse-T shaped silicon region formed over the semiconductor substrate, wherein the inverse-T shaped silicon region is approximately disposed within the area of the channel region; and a sidewall insulating region abutting to a sidewall of the inverse-T shaped silicon region. A first conductive region is formed on the top surface of the inverse-T shaped silicon region, and a second conductive region is formed on the top surface of the source region. Also, a third conductive region is formed on the top surface of the drain region.

Abstract: The MOSFETS structure includes a field oxide region formed on a silicon substrate. A gate includes a silicon dioxide layer formed on the silicon substrate, a first conductive layer formed on the silicon dioxide layer, a second oxide layer formed on the silicon dioxide layer and abutting to the first conductive layer and a first silicide layer formed on the first conductive layer and the second oxide layer. A pad oxide layer is formed on the silicon substrate and abutting to the silicon dioxide layer. An extended source/drain junction is formed under the pad oxide layer and abutting to the pad oxide layer, wherein one side of the extended source/drain junction is aligned with one side of the first conductive layer. A second silicide layer is formed between the field oxide region and the pad oxide layer, wherein the second silicide layer abutting to the field oxide region and the pad oxide layer. A first metal layer is formed right under the second silicide layer and aligned with the second silicide layer.

Abstract: The MOSFET has a stacked gate structure which has a first silicon layer, a second silicon layer, and a spacer structure. The first silicon layer is formed over the semiconductor substrate. The second silicon layer contains second type dopants and is formed on the first silicon layer. The spacer structure containing first type dopants is formed on the sidewall of the first silicon layer and the second silicon layer. A gate insulator layer is formed between the first silicon layer and the semiconductor substrate. The second silicon layer is also formed on the semiconductor substrate at a region uncovered by the stacked gate structure. A junction region is formed in the semiconductor substrate under the second silicon layer but not under the stacked gate structure. An extended junction is formed in the semiconductor substrate under the spacer structure.