Abstract: An augmented reality display unit for use in an augmented reality headset or the like comprising front and rear variable focusing power compression liquid lens assemblies (220, 230) in mutual optical alignment on an optical axis (O), a transparent waveguide display (240) interposed between the front and rear liquid lens assemblies (220, 230) and a selectively operable adjustment mechanism for adjusting the focusing powers of the front and rear compression liquid lens assemblies (220, 230); wherein each of the front and rear compression liquid lens assemblies (220, 230) comprises a fluid-filled envelope (225, 235) having a first wall formed by a distensible elastic membrane (226, 236) that is held under tension around its edge by a peripheral support ring, a second substantially rigid wall (223, 233) formed by or supported on an inner surface of a transparent plate or a hard lens of fixed focusing power, and a collapsible side wall (227, 237), the membrane forming an optical surface of variable optical power,

Abstract: An electrosurgical apparatus comprising an electrosurgical forceps instrument that combines la robust jaw opening mechanism with an a microwave energy delivery mechanism. The instrument includes a rigid bracket mounted at a distal end of a flexible shaft, wherein a pair of jaws are pivotably mounted on the rigid bracket. The instrument includes an energy delivery structure comprising a flexible dielectric substrate having a first electrode and an second electrode formed on one of the pair of jaws, wherein the first electrode and the second electrode are arranged to emit microwave energy. The electrosurgical apparatus may also comprise a handpiece that combines rotation control of an electrosurgical instrument with both power delivery and end effector actuation (e.g. jaw closure, blade retraction or the like).

Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

Abstract: The disclosure refers to a method for producing a coated plastic article, the method comprising: nnnnn. providing a plastic substrate having at least a first and second surface; ooooo. depositing on the plastic substrate a decorative coating comprising a metal or metal alloy layer, using physical vapor deposition; and ppppp. applying a protective coating to at least the first surface of the plastic article, wherein there is no plasma pre-treatment of the plastic substrate prior to deposition of the decorative coating. Further, the disclosure refers to a coated plastic article comprising; a plastic substrate having a first and second surface, a decorative coating comprising a metal or metal alloy layer deposited directly on the plastic substrate and a protective coating applied to the first surface of the plastic article, wherein the residual stress of the decorative coating is tensile, and the coated plastic article passes the SAEJ2527 accelerated UV test.

Abstract: A system performs static program analysis with artifact reuse. The system identifies artifacts associated with the software program being analyzed. The system processes the identified artifacts for performing static program analysis and transmits either the artifacts or identifiers for the artifacts to a second processing device for performing program analysis. The second processing device receives the artifacts and uses the received identifiers to retrieve the artifacts from a networked storage system. The second device also retrieves stored summaries of previous program analysis from the networked storage system. The program analysis uses the retrieved artifacts to generate work units for static program analysis. The analysis is performed only for those work units that are determined to remain unchanged from previous static program analysis cycles.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: An interactive toy comprising a function device for performing user-perceptible, controllable functions. The interactive toy also includes a rechargeable power source and a charging circuit for contactless receipt of electrical energy and for charging the rechargeable power source when the interactive toy is positioned in a charging zone of a contactless charging device. The interactive toy is adapted to determine a charging rate at respective positions relative to the charging device and to generate a user-perceptible output indicative of the determined charging rate.

Abstract: A physical space contains stationary objects that do not move over time (e.g., a couch) and may have non-stationary objects that do move over time (e.g., people and pets). An autonomous mobile device (AMD) determines and uses an occupancy map of stationary objects to find a route from one point to another in a physical space. Non-stationary objects are detected and prevented from being incorrectly added to the occupancy map. Point cloud data is processed to determine first candidate objects. Image data is processed to determine second candidate objects. These candidate objects are associated with each other and their characteristics assessed to determine if the candidate objects are stationary or non-stationary. The occupancy map is updated with stationary obstacles. During navigation, the occupancy map may be used for route planning while the non-stationary objects are used for local avoidance.

Abstract: A test system for testing a device having a plurality of electrical contacts. The test system comprising: a device table operable to hold at least one device under test, a probe comprising at least one probe end for contacting electrical contacts of a device under test, a movement mechanism operable to move one or both of the device table and the probe so as to bring the at least one probe end into contact with at least one electrical contact of a device under test, and a profile determining system configured to determine a profile of the electrical contacts of a device under test.

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Abstract: An autonomous mobile device (AMD) may move around a physical space while performing tasks. Sensor data is used to determine an occupancy map of the physical space. Some objects within the physical space may be difficult to detect because of characteristics that result in lower confidence in sensor data, such as transparent or reflective objects. To include difficult-to-detect objects in the occupancy map, image data is processed to identify portions of the image that includes features associated with difficult-to-detect objects. Given the portion that possibly includes difficult-to-detect objects, the AMD attempts to determine where in the physical space that portion corresponds to. For example, the AMD may use stereovision to determine the physical area associated with the features depicted in the portion. Objects in that area are included in an occupancy map annotated as objects that should persist unless confirmed to not be within the physical space.

Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.

Abstract: Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.