Patents by Inventor Simon Edwards
Simon Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250015086Abstract: Electronic circuits and methods encompassing an RF switch comprising a plurality of series-coupled (stacked) integrated circuit (IC) SOI MOSFETs having a distributed back-bias network structure comprising groups of substrate contacts coupled to a bias voltage source through a resistive ladder. The distributed back-bias network structure sets the common IC substrate voltage at a fixed DC bias but resistively decouples groups of MOSFETs with respect to RF voltages so that the voltage division characteristics of the MOSFET stack are maintained. The distributed back-bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET is effective as a switch device, while mitigating loss, leakage, crosstalk, and distortion. RF switches in accordance with the present invention are particularly useful as antenna switches.Type: ApplicationFiled: July 18, 2024Publication date: January 9, 2025Inventor: Simon Edward Willard
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Patent number: 12182149Abstract: Visual search in an operating system of a computing device can process and provide additional information on the content being provided for display. The computing device can include an operating system that includes a visual search interface that obtains and processes display data associated with content currently being provided for display. The visual search interface can generate display data based on the current content provided for display, process the display data with one or more on-device machine-learned models, and provide additional information to the user. The visual search interface may transmit data associated with the display data to perform additional data processing tasks. Application suggestions may be determined and provided based on the visual search data.Type: GrantFiled: October 13, 2023Date of Patent: December 31, 2024Assignee: GOOGLE LLCInventors: Golden Gopal Krishna, Shadia Walsh, Rosemary Margaret La Prairie, Carsten Hinz, Simon Edward Roberts, Sarah Fay Smith, Stacy Lou Chiou, Zhipeng Pan, Clement Dickinson Wright
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Publication number: 20240429239Abstract: Structures and methods for better optimizing the performance of all the circuitry of an SOI IC. Embodiments include SOI IC having dual-thickness active areas, such that digital and non-RF analog circuitry may be fabricated on a relatively thin active layer while RF circuitry may be fabricated on a relatively thick active layer. Fabrication of RF circuitry on the relatively thick active layer allows for improvements to the RON*COFF figure of merit for the FET devices, and for optimizations not feasible for RF circuitry fabricated on a relatively thin active layer. Two methods of forming shallow-trench isolation (STI) structures in both active layers are described. A first method forms STIs in the thin active layer first, then in the thick active layer. A second method forms STIs in the thin active layer first and partial STIs in the thick active layer, then completes the partial STIs in the thick active layer.Type: ApplicationFiled: June 22, 2023Publication date: December 26, 2024Inventors: Jagar Singh, Kazuhiko Shibata, Simon Edward Willard
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Publication number: 20240425595Abstract: The present disclosure relates to novel PD-1 binding domains that have a higher binding affinity for human PD-1 than a reference PD-1 binding domain. The PD-1 binding domains of the present disclosure further provide a comparable, or equal or higher, potency in blocking ligand binding to human PD-1 than a reference PD-1 antibody. The present disclosure further relates to binding moieties comprising such PD-1 binding domains. Also provided is a method for treating a disease, in particular a disease associated with a suppressed immune system, such as cancer, with a PD-1 binding domain or binding moiety of the present disclosure. The present disclosure further relates to nucleic acids encoding the heavy chain variable region of the PD-1 binding domains, and a vector and cell comprising such nucleic acid.Type: ApplicationFiled: April 3, 2024Publication date: December 26, 2024Applicants: MERUS N.V., INCYTE CORPORATIONInventors: Simon Edward PLYTE, Patrick MAYES, Horacio G. NASTRI, Shaun M. STEWART, Rebecca A. BUONPANE
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Publication number: 20240425594Abstract: The present disclosure relates to novel PD-1 binding domains that have a higher binding affinity for human PD-1 than a reference PD-1 binding domain. The PD-1 binding domains of the present disclosure further provide a comparable, or equal or higher, potency in blocking ligand binding to human PD-1 than a reference PD-1 antibody. The present disclosure further relates to binding moieties comprising such PD-1 binding domains. Also provided is a method for treating a disease, in particular a disease associated with a suppressed immune system, such as cancer, with a PD-1 binding domain or binding moiety of the present disclosure. The present disclosure further relates to nucleic acids encoding the heavy chain variable region of the PD-1 binding domains, and a vector and cell comprising such nucleic acid.Type: ApplicationFiled: April 3, 2024Publication date: December 26, 2024Applicants: MERUS N.V., INCYTE CORPORATIONInventors: Simon Edward PLYTE, Patrick MAYES, Horacio G. NASTRI, Shaun M. STEWART, Rebecca A. BUONPANE
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Publication number: 20240413243Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.Type: ApplicationFiled: June 24, 2024Publication date: December 12, 2024Inventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
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Publication number: 20240388289Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.Type: ApplicationFiled: March 25, 2024Publication date: November 21, 2024Inventor: Simon Edward WILLARD
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Publication number: 20240347482Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.Type: ApplicationFiled: March 22, 2024Publication date: October 17, 2024Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
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Publication number: 20240339032Abstract: A device for controlling in-vehicle signage is disposed to provide a physical indication of a particular in-vehicle sign. The data defining the particular sign is associated with data defining a trigger point for causing the occurrence of the indication of the particular sign. The device is adapted for control by a processor that is responsive to a conflict between the particular sign and at least one of another sign or a message and is disposed to alter the data defining the trigger point to remove the conflict. The trigger point is defined by the intersection of the path of a vehicle and a trigger zone extending spatially from a defined location of the particular sign.Type: ApplicationFiled: August 4, 2022Publication date: October 10, 2024Inventors: Damian Andrew Horton, Marcus Simon Edward Robbins, Anna Rachel Corp
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Publication number: 20240340004Abstract: Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.Type: ApplicationFiled: June 20, 2024Publication date: October 10, 2024Inventors: Eric S. SHAPIRO, Simon Edward WILLARD
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Patent number: 12108188Abstract: One example method for integrating software application content into video conferences includes receiving, by a video conferencing application executed by a client device from a video conference provider, one or more participant video streams, each participant video stream corresponding to a participant in a video conference; receiving, by the video conferencing application from a software application, software application content; receiving, by the video conferencing application from the software application, display layout information; generating, by the video conferencing application, a graphical representation of the video conference according to the display layout information, the graphical representation comprising at least a portion of the software application content and at least one of the one or more participant video streams; and displaying, by the video conferencing application, the graphical representation of the video conference.Type: GrantFiled: August 26, 2022Date of Patent: October 1, 2024Assignee: Zoom Video Communications, Inc.Inventors: Simon Edward Booth, Raghavendra Bhagavatha, Roger Dean Collins, Andy Hendrickson, Corey Hobbs, Arun Janakiraman, Shengwu Zhou
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Patent number: 12100707Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: GrantFiled: August 9, 2023Date of Patent: September 24, 2024Assignee: pSemi CorporationInventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Patent number: 12100734Abstract: FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ?MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ?MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.Type: GrantFiled: October 6, 2022Date of Patent: September 24, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
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Publication number: 20240309115Abstract: The present disclosure relates to a multispecific antibody comprising a binding domain that binds to LAG-3 and a binding domain that binds to PD-L1. Such multispecific antibody has comparable, or equal or higher, potency than a combination of LAG-3 and PD-L1 reference antibodies. Also provided is a method for treating a disease, in particular a disease associated with a suppressed immune system, such as cancer, with a multispecific antibody of the present disclosure. The present disclosure further relates to a vector and cell comprising nucleic acids encoding the heavy chain variable region of the LAG-3 and PD-L1 binding domains.Type: ApplicationFiled: March 30, 2022Publication date: September 19, 2024Inventors: Simon Edward PLYTE, Cornelis Adriaan DE KRUIF
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Publication number: 20240313081Abstract: FET designs, and in particular NMOSFET designs based on SOI fabrication technology, that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments include FETs in which the threshold voltage VTE of the edge FETs is increased to a level that is at least equal to the threshold voltage VTC of the central conduction channel FET using a novel dual work function configuration of a high dielectric constant (high-?) replacement metal gate (RMG) structure. One embodiment encompasses a FET including an RMG structure overlying a doped silicon region, the RMG structure including: an interface insulator formed over the doped silicon region; a high-? material formed over the interface insulator; an N-type work function material overlaying and in contact with a central portion of the high-? material; and a P-type work function material overlaying and in contact with at least one edge portion of the high-? material.Type: ApplicationFiled: March 16, 2023Publication date: September 19, 2024Inventors: Jagar Singh, Simon Edward Willard
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Patent number: 12057827Abstract: Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.Type: GrantFiled: December 27, 2022Date of Patent: August 6, 2024Assignee: pSemi CorporationInventors: Eric S. Shapiro, Simon Edward Willard
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Patent number: 12051701Abstract: Electronic circuits and methods encompassing an RF switch comprising a plurality of series-coupled (stacked) integrated circuit (IC) SOI MOSFETs having a distributed back-bias network structure comprising groups of substrate contacts coupled to a bias voltage source through a resistive ladder. The distributed back-bias network structure sets the common IC substrate voltage at a fixed DC bias but resistively decouples groups of MOSFETs with respect to RF voltages so that the voltage division characteristics of the MOSFET stack are maintained. The distributed back-bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET is effective as a switch device, while mitigating loss, leakage, crosstalk, and distortion. RF switches in accordance with the present invention are particularly useful as antenna switches.Type: GrantFiled: June 20, 2022Date of Patent: July 30, 2024Assignee: pSemi CorporationInventor: Simon Edward Willard
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Patent number: 12027623Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.Type: GrantFiled: February 4, 2021Date of Patent: July 2, 2024Assignee: Murata Manufacturing Co., LtdInventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
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Patent number: 11993654Abstract: The present disclosure relates to novel PD-1 binding domains that have a higher binding affinity for human PD-1 than a reference PD-1 binding domain. The PD-1 binding domains of the present disclosure further provide a comparable, or equal or higher, potency in blocking ligand binding to human PD-1 than a reference PD-1 antibody. The present disclosure further relates to binding moieties comprising such PD-1 binding domains. Also provided is a method for treating a disease, in particular a disease associated with a suppressed immune system, such as cancer, with a PD-1 binding domain or binding moiety of the present disclosure. The present disclosure further relates to nucleic acids encoding the heavy chain variable region of the PD-1 binding domains, and a vector and cell comprising such nucleic acid.Type: GrantFiled: March 31, 2022Date of Patent: May 28, 2024Assignees: MERUS N.V., INCYTE CORPORATIONInventors: Simon Edward Plyte, Patrick Mayes, Horacio G. Nastri, Shaun M. Stewart, Rebecca A. Buonpane
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Patent number: D1046827Type: GrantFiled: March 5, 2020Date of Patent: October 15, 2024Assignee: Tait International LimitedInventors: Martin Stewart McKendry, Xiaohan Wang, Simon Edward Pollard