Patents by Inventor Simon Edwards

Simon Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791340
    Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: October 17, 2023
    Assignee: pSemi Corporation
    Inventor: Simon Edward Willard
  • Publication number: 20230283237
    Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 7, 2023
    Inventors: Simon Edward Willard, Chris Olson, Tero Tapio Ranta
  • Patent number: 11742802
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: August 29, 2023
    Assignee: pSemi Corporation
    Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
  • Patent number: 11735589
    Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: August 22, 2023
    Assignee: pSemi Corporation
    Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
  • Publication number: 20230246643
    Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 3, 2023
    Inventor: Simon Edward WILLARD
  • Publication number: 20230208417
    Abstract: Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 29, 2023
    Inventors: Eric S. SHAPIRO, Simon Edward WILLARD
  • Patent number: 11684792
    Abstract: A device (200) which includes a monitoring unit (210), a therapy unit (220), and a display (100) that includes a touch screen (110). The monitoring unit (210) can be configured to monitor a person's vital signs, such as a person's electrocardiogram (ECG). The therapy unit (220) can be configured to administer an electric shock. The display (100) can be configured to display the ECG and enable a user to scroll the displayed ECG back and forth and/or to zoom in and zoom out the displayed ECG by touching the touch screen (110). The display (100) can also be configured to enable the user to select two or more separate segments of the ECG to view together at the same time on the display (100), which segments can be separated by intervening segments of the ECG that can be hidden from being viewed on the display (100). The display (100) can have multiple user-interface windows (120, 130).
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 27, 2023
    Assignee: Koninklijke Philips N.V.
    Inventors: Patrick Guiney, William Douglas Grube, John Mardirosian, Scott Alan Wuthrich, Simon Edward Kozin
  • Publication number: 20230190820
    Abstract: The invention generally relates to cells and compositions comprising same for use in cell therapy, to methods of obtaining same, and to use of same in cell therapy. In one aspect, the invention provides a method for forming a cell composition from a tissue sample, the method comprising: providing a tissue sample comprising cells; contacting the sample with a polymer in binding conditions, said binding conditions being conditions that enable binding of cells in the sample to the polymer, so that said cells are bound to the polymer; culturing the cells bound to the polymer under conditions and for a time that allows the cell number to increase; providing conditions to induce a phase change of the polymer; thereby forming a cell composition from a tissue sample.
    Type: Application
    Filed: May 27, 2021
    Publication date: June 22, 2023
    Inventors: Peter F.M. Choong, Sam Lourdesan Francis, Serena Duchi, Carmine Onofrillo, Claudia Di Bella, Sanjeev Gambhir, Simon Edward Moulton, Christopher Halkias, Cathal D. O'Connell, Nicholas Paul Reynolds, Gordon George Wallace
  • Patent number: 11673786
    Abstract: Various aspects of the invention described herein relate to a removable connector assembly, and methods of use and manufacture thereof. More particularly, certain embodiments relate to apparatus and methods to provide a connection to a spout disposed upon a container, such as upon a bag holding fluid. Embodiments of connector assemblies comprise an elongated outer housing, an inner housing, and a slider assembly for moving the outer surface of the sleeve member over the inner surface of the outer housing wall in a lengthwise motion to position the spout connector upon the spout and secure the spout connector in said position.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 13, 2023
    Assignee: Ourip Pty Ltd.
    Inventor: Simon Edwards
  • Patent number: 11673723
    Abstract: The invention described herein relates broadly to closure assemblies, and methods of use and manufacture thereof. More particularly, certain embodiments relate to assemblies and methods for closing an opening defined by a spout provided on a flexible container utilising a capping member having a plugging portion and a substantially fracturable retaining skirt. Embodiments provide may an adequate seal for the contents contained within bags against the significant pressure placed upon the closure by the often weighty and voluminous contents of the packaging. Furthermore, the closure may be easily and comfortably removable by a user whilst managing the handling of the bag.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 13, 2023
    Assignee: Ourip Pty Ltd.
    Inventor: Simon Edwards
  • Publication number: 20230094494
    Abstract: FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ?MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ?MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.
    Type: Application
    Filed: October 6, 2022
    Publication date: March 30, 2023
    Inventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
  • Publication number: 20230082886
    Abstract: One example method for integrating software application content into video conferences includes receiving, by a video conferencing application executed by a client device from a video conference provider, one or more participant video streams, each participant video stream corresponding to a participant in a video conference; receiving, by the video conferencing application from a software application, software application content; receiving, by the video conferencing application from the software application, display layout information; generating, by the video conferencing application, a graphical representation of the video conference according to the display layout information, the graphical representation comprising at least a portion of the software application content and at least one of the one or more participant video streams; and displaying, by the video conferencing application, the graphical representation of the video conference.
    Type: Application
    Filed: August 26, 2022
    Publication date: March 16, 2023
    Applicant: Zoom Video Communications, Inc.
    Inventors: Simon Edward BOOTH, Raghavendra Bhagavatha, Roger Dean Collins, Andy Hendrickson, Corey Hobbs, Arun Janakiraman, Shengwu Zhou
  • Patent number: 11606065
    Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 14, 2023
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Chris Olson, Tero Tapio Ranta
  • Patent number: 11601126
    Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: March 7, 2023
    Assignee: PSEMI CORPORATION
    Inventor: Simon Edward Willard
  • Publication number: 20230065101
    Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.
    Type: Application
    Filed: July 6, 2022
    Publication date: March 2, 2023
    Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
  • Publication number: 20230036061
    Abstract: The present disclosure relates to novel PD-1 binding domains that have a higher binding affinity for human PD-1 than a reference PD-1 binding domain. The PD-1 binding domains of the present disclosure further provide a comparable, or equal or higher, potency in blocking ligand binding to human PD-1 than a reference PD-1 antibody. The present disclosure further relates to binding moieties comprising such PD-1 binding domains. Also provided is a method for treating a disease, in particular a disease associated with a suppressed immune system, such as cancer, with a PD-1 binding domain or binding moiety of the present disclosure. The present disclosure further relates to nucleic acids encoding the heavy chain variable region of the PD-1 binding domains, and a vector and cell comprising such nucleic acid.
    Type: Application
    Filed: March 31, 2022
    Publication date: February 2, 2023
    Inventors: Simon Edward PLYTE, Patrick MAYES, Horacio G. NASTRI, Shaun M. STEWART, Rebecca A. BUONPANE
  • Publication number: 20230032891
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 2, 2023
    Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
  • Patent number: 11569812
    Abstract: Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: January 31, 2023
    Assignee: PSEMI CORPORATION
    Inventors: Eric S. Shapiro, Simon Edward Willard
  • Patent number: D988332
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 6, 2023
    Assignee: RASPBERRY PI (TRADING) LIMITED
    Inventor: Simon Edward Martin
  • Patent number: D988379
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 6, 2023
    Assignee: RASPBERRY PI (TRADING) LIMITED
    Inventor: Simon Edward Martin