Patents by Inventor Simon Edwards
Simon Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11547632Abstract: Embodiments of a medical vial holder apparatus and system are disclosed. A main body has a mount engagement portion and a vial engagement portion. A facing wall is attached to the vial engagement portion thereby defining a vial retention cavity therebetween. A lever element is mounted to the main body for pivotal movement between a grip position and a release position. The lever element has a grip portion with a vial engagement face. A grip distance is defined between the vial engagement face and the facing wall. Movement of the lever element from the release position toward the grip position reduces the grip distance. Movement of the lever element from the grip position toward the release position increases the grip distance. The lever element is biased toward the grip position. A plurality of the apparatuses are adjustably mountable in line with one another by way of their mount engagement portions.Type: GrantFiled: August 1, 2020Date of Patent: January 10, 2023Assignee: TBM Medical Solutions, Inc.Inventors: David Peter Carter, Simon Edward Morse
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Publication number: 20220367522Abstract: Electronic circuits and methods encompassing an RF switch comprising a plurality of series-coupled (stacked) integrated circuit (IC) SOI MOSFETs having a distributed back-bias network structure comprising groups of substrate contacts coupled to a bias voltage source through a resistive ladder. The distributed back-bias network structure sets the common IC substrate voltage at a fixed DC bias but resistively decouples groups of MOSFETs with respect to RF voltages so that the voltage division characteristics of the MOSFET stack are maintained. The distributed back-bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET is effective as a switch device, while mitigating loss, leakage, crosstalk, and distortion. RF switches in accordance with the present invention are particularly useful as antenna switches.Type: ApplicationFiled: June 20, 2022Publication date: November 17, 2022Inventor: Simon Edward Willard
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Publication number: 20220363761Abstract: The present disclosure relates to multispecific binding moieties comprising novel PD-1 binding domains that have a higher binding affinity for human PD-1 than a reference PD-1 binding domain. Such multispecific binding moieties further provide a comparable, or equal or higher, potency in blocking ligand binding to human PD-1 than a reference PD-1 antibody. The present disclosure in particular relates to multispecific binding moieties comprising a novel PD-1 binding domain and a LAG-3 binding domain. Also provided is a method for treating a disease, in particular a disease associated with a suppressed immune system, such as cancer, with a multispecific binding moiety of the present disclosure. The present disclosure further relates to a vector and cell comprising nucleic acids encoding a novel PD-1 binding domain and a LAG-3 binding domain.Type: ApplicationFiled: March 30, 2022Publication date: November 17, 2022Inventors: Simon Edward PLYTE, Patrick MAYES, Horacio G. NASTRI, Shaun M. STEWART
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Patent number: 11495927Abstract: One variation of a portable radio system includes: a portable radio configured to transmit and receive audio communication, including a connector receptacle arranged on a rear face of the portable radio and a channel extending from the connector receptacle; a cable, configured to couple the portable radio to a secondary device, including a straight section configured to seat within the channel and defining a length greater than a length of the channel; a connector, coupled to the straight section of the cable, configured to seat within the connector receptacle to couple the cable to the portable radio in an upward and downward orientation; and a clip including a base section configured to transiently couple to the body over the connector and a clamp section configured to pivot relative the base section and to attach the portable radio to a user.Type: GrantFiled: November 25, 2020Date of Patent: November 8, 2022Assignee: Tait International LimitedInventors: Cameron Patrick Greig O'Keeffe, Justin Allan Standring, Simon Edward Pollard, Sasha Wang, Reece Boyd Browne
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Patent number: 11469296Abstract: FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ?MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ?MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.Type: GrantFiled: July 15, 2020Date of Patent: October 11, 2022Assignee: pSemi CorporationInventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
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Publication number: 20220313555Abstract: Embodiments of a medical vial holder apparatus and system are disclosed. A main body has a mount engagement portion and a vial engagement portion. A facing wall is attached to the vial engagement portion thereby defining a vial retention cavity therebetween. A lever element is mounted to the main body for pivotal movement between a grip position and a release position. The lever element has a grip portion with a vial engagement face. A grip distance is defined between the vial engagement face and the facing wall. Movement of the lever element from the release position toward the grip position reduces the grip distance. Movement of the lever element from the grip position toward the release position increases the grip distance. The lever element is biased toward the grip position. A plurality of the apparatuses are adjustably mountable in line with one another by way of their mount engagement portions.Type: ApplicationFiled: August 1, 2020Publication date: October 6, 2022Inventors: David Peter Carter, Simon Edward Morse
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Patent number: 11460854Abstract: An autonomous mobile device (AMD) moving in a physical space determines the presence of obstacles using images acquired by a stereocamera and avoids those obstacles. A floor with few visible features is difficult to characterize. The floor and any obstacles thereon may be difficult to characterize due to noise, perspective effect, and so forth. A score is determined that indicates whether a particular pixel in an image is deemed to be associated with a parallel surface (the floor) or a perpendicular surface (an obstacle). The score is computationally inexpensive to calculate and allows for highly accurate and low latency determinations as to the presence of an obstacle that would impede movement of the AMD. Orientation changes in the AMD, such as movement over a bumpy floor, are well tolerated as are floor features such as flooring transitions, ramps, and so forth which the AMD is able to traverse.Type: GrantFiled: April 28, 2020Date of Patent: October 4, 2022Assignee: Amazon Technologies, Inc.Inventors: Mark Adcock, Simon Edwards-Parton
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Publication number: 20220300001Abstract: A physical space contains stationary objects that do not move over time (e.g., a couch) and may have non-stationary objects that do move over time (e.g., people and pets). An autonomous mobile device (AMD) determines and uses an occupancy map of stationary objects to find a route from one point to another in a physical space. Non-stationary objects are detected and prevented from being incorrectly added to the occupancy map. Point cloud data is processed to determine first candidate objects. Image data is processed to determine second candidate objects. These candidate objects are associated with each other and their characteristics assessed to determine if the candidate objects are stationary or non-stationary. The occupancy map is updated with stationary obstacles. During navigation, the occupancy map may be used for route planning while the non-stationary objects are used for local avoidance.Type: ApplicationFiled: March 19, 2021Publication date: September 22, 2022Inventors: SHREEKANT GAYAKA, BOSHEN NIU, SIMON EDWARDS-PARTON
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Patent number: 11418183Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: GrantFiled: May 20, 2021Date of Patent: August 16, 2022Assignee: pSemi CorporationInventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
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Publication number: 20220246550Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.Type: ApplicationFiled: February 11, 2022Publication date: August 4, 2022Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
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Patent number: 11387235Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: GrantFiled: August 19, 2020Date of Patent: July 12, 2022Assignee: pSemi CorporationInventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Patent number: 11374022Abstract: Electronic circuits and methods encompassing an RF switch comprising a plurality of series-coupled (stacked) integrated circuit (IC) SOI MOSFETs having a distributed back-bias network structure comprising groups of substrate contacts coupled to a bias voltage source through a resistive ladder. The distributed back-bias network structure sets the common IC substrate voltage at a fixed DC bias but resistively decouples groups of MOSFETs with respect to RF voltages so that the voltage division characteristics of the MOSFET stack are maintained. The distributed back-bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET is effective as a switch device, while mitigating loss, leakage, crosstalk, and distortion. RF switches in accordance with the present invention are particularly useful as antenna switches.Type: GrantFiled: June 14, 2019Date of Patent: June 28, 2022Assignee: pSemi CorporationInventor: Simon Edward Willard
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Publication number: 20220190826Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.Type: ApplicationFiled: December 11, 2020Publication date: June 16, 2022Inventor: Simon Edward WILLARD
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Patent number: 11362351Abstract: An apparatus (10) configured to determine reactant purity comprising: a first fuel cell (11) configured to generate electrical current from the electrochemical reaction between two reactants, having a first reactant inlet (13) configured to receive a test reactant comprising one of the two reactants from a first reactant source (7, 5, 16); a second fuel cell (12) configured to generate electrical current from the electrochemical reaction between the two reactants, having a second reactant inlet (14) configured to receive the test reactant from a second reactant source (5); a controller (20) configured to apply an electrical load to each fuel cell and determine an electrical output difference, ODt, between an electrical output of the first fuel cell (11) and an electrical output of the second fuel cell (12), and determine a difference between a predicted output difference and the determined electrical output difference, ODt, the predicted output difference determined based on a historical output of differenceType: GrantFiled: November 13, 2020Date of Patent: June 14, 2022Assignee: Intelligent Energy LimitedInventors: Michael John Provost, Kevin M. Kupcho, Simon Edward Foster, Ashley James Kells
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Patent number: 11345586Abstract: A tap assembly for reducing the infiltration of fluid from the exterior of a fluid container to the interior of a fluid container comprising a tap valve, a valve closure, and a hollow tap body. The tap body provides a fluid outlet for allowing the passage of fluid through the tap assembly and a multi-start male thread to slidably move the valve closure from an open position to a closed position. The tap assembly further comprises three concentric securement pieces configured to interface with the fluid container and form a three-point locking mechanism interlocking the three concentric securement pieces.Type: GrantFiled: April 20, 2020Date of Patent: May 31, 2022Assignee: Ourip Pty LtdInventor: Simon Edwards
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Publication number: 20220158589Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.Type: ApplicationFiled: November 19, 2021Publication date: May 19, 2022Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
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Patent number: 11335704Abstract: Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects.Type: GrantFiled: July 7, 2020Date of Patent: May 17, 2022Assignee: pSemi CorporationInventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet, Ronald Eugene Reedy
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Publication number: 20220118160Abstract: An implantable device and methods for preparing and implanting said device into a subject for use in treating a medical condition when implanted therein is disclosed. The device comprises at least one coaxial fibre of a hydrophilic polymer and a hydrophobic polymer, wherein at least one of said polymers is loaded with an agent that is active towards treating the medical condition.Type: ApplicationFiled: September 23, 2019Publication date: April 21, 2022Inventors: Kara Lea PERROW, Samantha Jane WADE, Simon Edward MOULTON, Sepehr TALEBIAN, Javad FOROUGHI, Morteza AGHMESHEH, Gordon George WALLACE
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Publication number: 20220089428Abstract: Embodiments relate to a tap assembly for reducing the infiltration of fluid from the exterior of a fluid container to the interior of a fluid container comprising a tap valve, a valve closure, and a hollow tap body. The tap body provides a fluid outlet for allowing the passage of fluid through the tap assembly and a multi-start male thread to slidably move the valve closure from an open position to a closed position. The tap assembly further comprises three concentric securement pieces configured to interface with the fluid container and form a three-point locking mechanism interlocking the three concentric securement pieces.Type: ApplicationFiled: April 20, 2020Publication date: March 24, 2022Applicant: Ourip Pty LtdInventor: Simon EDWARDS
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Patent number: 11251140Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.Type: GrantFiled: May 15, 2020Date of Patent: February 15, 2022Assignee: pSemi CorporationInventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard