Patents by Inventor Simon Edwards

Simon Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11993654
    Abstract: The present disclosure relates to novel PD-1 binding domains that have a higher binding affinity for human PD-1 than a reference PD-1 binding domain. The PD-1 binding domains of the present disclosure further provide a comparable, or equal or higher, potency in blocking ligand binding to human PD-1 than a reference PD-1 antibody. The present disclosure further relates to binding moieties comprising such PD-1 binding domains. Also provided is a method for treating a disease, in particular a disease associated with a suppressed immune system, such as cancer, with a PD-1 binding domain or binding moiety of the present disclosure. The present disclosure further relates to nucleic acids encoding the heavy chain variable region of the PD-1 binding domains, and a vector and cell comprising such nucleic acid.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: May 28, 2024
    Assignees: MERUS N.V., INCYTE CORPORATION
    Inventors: Simon Edward Plyte, Patrick Mayes, Horacio G. Nastri, Shaun M. Stewart, Rebecca A. Buonpane
  • Patent number: 11973495
    Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 30, 2024
    Assignee: pSemi Corporation
    Inventor: Simon Edward Willard
  • Publication number: 20240113126
    Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 4, 2024
    Inventor: Simon Edward Willard
  • Patent number: 11948897
    Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 2, 2024
    Assignee: pSemi Corporation
    Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
  • Publication number: 20240088151
    Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.
    Type: Application
    Filed: August 9, 2023
    Publication date: March 14, 2024
    Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
  • Patent number: 11927963
    Abstract: A physical space contains stationary objects that do not move over time (e.g., a couch) and may have non-stationary objects that do move over time (e.g., people and pets). An autonomous mobile device (AMD) determines and uses an occupancy map of stationary objects to find a route from one point to another in a physical space. Non-stationary objects are detected and prevented from being incorrectly added to the occupancy map. Point cloud data is processed to determine first candidate objects. Image data is processed to determine second candidate objects. These candidate objects are associated with each other and their characteristics assessed to determine if the candidate objects are stationary or non-stationary. The occupancy map is updated with stationary obstacles. During navigation, the occupancy map may be used for route planning while the non-stationary objects are used for local avoidance.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 12, 2024
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Shreekant Gayaka, Boshen Niu, Simon Edwards-Parton
  • Publication number: 20240063785
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
    Type: Application
    Filed: September 13, 2023
    Publication date: February 22, 2024
    Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
  • Publication number: 20240039479
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 1, 2024
    Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
  • Patent number: 11870431
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: January 9, 2024
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
  • Patent number: 11797022
    Abstract: An autonomous mobile device (AMD) may move around a physical space while performing tasks. Sensor data is used to determine an occupancy map of the physical space. Some objects within the physical space may be difficult to detect because of characteristics that result in lower confidence in sensor data, such as transparent or reflective objects. To include difficult-to-detect objects in the occupancy map, image data is processed to identify portions of the image that includes features associated with difficult-to-detect objects. Given the portion that possibly includes difficult-to-detect objects, the AMD attempts to determine where in the physical space that portion corresponds to. For example, the AMD may use stereovision to determine the physical area associated with the features depicted in the portion. Objects in that area are included in an occupancy map annotated as objects that should persist unless confirmed to not be within the physical space.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: October 24, 2023
    Inventors: James Ballantyne, Eric Foxlin, Lu Xia, Simon Edwards-Parton, Boshen Niu, Harish Annavajjala
  • Patent number: 11791340
    Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: October 17, 2023
    Assignee: pSemi Corporation
    Inventor: Simon Edward Willard
  • Publication number: 20230283237
    Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 7, 2023
    Inventors: Simon Edward Willard, Chris Olson, Tero Tapio Ranta
  • Patent number: 11742802
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: August 29, 2023
    Assignee: pSemi Corporation
    Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
  • Patent number: 11735589
    Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: August 22, 2023
    Assignee: pSemi Corporation
    Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
  • Publication number: 20230246643
    Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 3, 2023
    Inventor: Simon Edward WILLARD
  • Publication number: 20230208417
    Abstract: Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 29, 2023
    Inventors: Eric S. SHAPIRO, Simon Edward WILLARD
  • Patent number: 11684792
    Abstract: A device (200) which includes a monitoring unit (210), a therapy unit (220), and a display (100) that includes a touch screen (110). The monitoring unit (210) can be configured to monitor a person's vital signs, such as a person's electrocardiogram (ECG). The therapy unit (220) can be configured to administer an electric shock. The display (100) can be configured to display the ECG and enable a user to scroll the displayed ECG back and forth and/or to zoom in and zoom out the displayed ECG by touching the touch screen (110). The display (100) can also be configured to enable the user to select two or more separate segments of the ECG to view together at the same time on the display (100), which segments can be separated by intervening segments of the ECG that can be hidden from being viewed on the display (100). The display (100) can have multiple user-interface windows (120, 130).
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 27, 2023
    Assignee: Koninklijke Philips N.V.
    Inventors: Patrick Guiney, William Douglas Grube, John Mardirosian, Scott Alan Wuthrich, Simon Edward Kozin
  • Publication number: 20230190820
    Abstract: The invention generally relates to cells and compositions comprising same for use in cell therapy, to methods of obtaining same, and to use of same in cell therapy. In one aspect, the invention provides a method for forming a cell composition from a tissue sample, the method comprising: providing a tissue sample comprising cells; contacting the sample with a polymer in binding conditions, said binding conditions being conditions that enable binding of cells in the sample to the polymer, so that said cells are bound to the polymer; culturing the cells bound to the polymer under conditions and for a time that allows the cell number to increase; providing conditions to induce a phase change of the polymer; thereby forming a cell composition from a tissue sample.
    Type: Application
    Filed: May 27, 2021
    Publication date: June 22, 2023
    Inventors: Peter F.M. Choong, Sam Lourdesan Francis, Serena Duchi, Carmine Onofrillo, Claudia Di Bella, Sanjeev Gambhir, Simon Edward Moulton, Christopher Halkias, Cathal D. O'Connell, Nicholas Paul Reynolds, Gordon George Wallace
  • Patent number: 11673786
    Abstract: Various aspects of the invention described herein relate to a removable connector assembly, and methods of use and manufacture thereof. More particularly, certain embodiments relate to apparatus and methods to provide a connection to a spout disposed upon a container, such as upon a bag holding fluid. Embodiments of connector assemblies comprise an elongated outer housing, an inner housing, and a slider assembly for moving the outer surface of the sleeve member over the inner surface of the outer housing wall in a lengthwise motion to position the spout connector upon the spout and secure the spout connector in said position.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 13, 2023
    Assignee: Ourip Pty Ltd.
    Inventor: Simon Edwards
  • Patent number: 11673723
    Abstract: The invention described herein relates broadly to closure assemblies, and methods of use and manufacture thereof. More particularly, certain embodiments relate to assemblies and methods for closing an opening defined by a spout provided on a flexible container utilising a capping member having a plugging portion and a substantially fracturable retaining skirt. Embodiments provide may an adequate seal for the contents contained within bags against the significant pressure placed upon the closure by the often weighty and voluminous contents of the packaging. Furthermore, the closure may be easily and comfortably removable by a user whilst managing the handling of the bag.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 13, 2023
    Assignee: Ourip Pty Ltd.
    Inventor: Simon Edwards