Patents by Inventor Simon Edwards
Simon Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10862146Abstract: An apparatus (10) configured to determine reactant purity comprising: a first fuel cell (11) configured to generate electrical current from the electrochemical reaction between two reactants, having a first reactant inlet (13) configured to receive a test reactant comprising one of the two reactants from a first reactant source (7, 5, 16); a second fuel cell (12) configured to generate electrical current from the electrochemical reaction between the two reactants, having a second reactant inlet (14) configured to receive the test reactant from a second reactant source (5); a controller (20) configured to apply an electrical load to each fuel cell and determine an electrical output difference, ODt, between an electrical output of the first fuel cell (11) and an electrical output of the second fuel cell (12), and determine a difference between a predicted output difference and the determined electrical output difference, ODt, the predicted output difference determined based on a historical output of differenceType: GrantFiled: May 5, 2015Date of Patent: December 8, 2020Inventors: Michael John Provost, Kevin M. Kupcho, Simon Edward Foster, Ashley James Kells
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Patent number: 10862473Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: GrantFiled: November 13, 2019Date of Patent: December 8, 2020Assignee: pSemi CorporationInventors: Tero Tapio Ranta, Simon Edward Willard
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Patent number: 10858082Abstract: A rotary cleaning apparatus for underwater cleaning including a housing, a battery, a motor and a flexible hub system. The flexible hub system includes a toroidal brush system coupled to a circular centrifugal pump assembly. The flexible hub system includes a flexible hub allowing the flexible hub system to bend out of plane. When the flexible hub system is rotated underwater at a curved surface, the brush system cleans the surface while the suction of the centrifugal pump assembly flexes the flexible hub system to evenly contact the surface.Type: GrantFiled: October 17, 2018Date of Patent: December 8, 2020Inventor: Simon Edward Smith
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Publication number: 20200358402Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.Type: ApplicationFiled: May 22, 2020Publication date: November 12, 2020Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
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Publication number: 20200350267Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.Type: ApplicationFiled: May 15, 2020Publication date: November 5, 2020Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
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Publication number: 20200335522Abstract: Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects.Type: ApplicationFiled: July 7, 2020Publication date: October 22, 2020Inventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet, Ronald Eugene Reedy
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Publication number: 20200321955Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGs is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGs type, or a mix of positive-logic and zero VGs type FETs with end-cap FETs of the zero VGs type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: ApplicationFiled: April 20, 2020Publication date: October 8, 2020Inventors: Simon Edward Willard, Tero Tapio Ranta
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Publication number: 20200303419Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.Type: ApplicationFiled: March 17, 2020Publication date: September 24, 2020Inventor: Simon Edward Willard
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Patent number: 10784818Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.Type: GrantFiled: June 26, 2019Date of Patent: September 22, 2020Assignee: pSemi CorporationInventors: Simon Edward Willard, Chris Olson, Tero Tapio Ranta
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Patent number: 10770480Abstract: Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.Type: GrantFiled: May 24, 2019Date of Patent: September 8, 2020Assignee: pSemi CorporationInventors: Buddhika Abesingha, Simon Edward Willard, Alain Duvallet, Merlin Green, Sivakumar Kumarasamy
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Patent number: 10763257Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: GrantFiled: September 24, 2019Date of Patent: September 1, 2020Assignee: pSemi CorporationInventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Patent number: 10750916Abstract: A cyclonic separator comprising a cyclone chamber defined between an outer wall and a shroud. The shroud comprises an inlet opening through which fluid enters the cyclone chamber, and a plurality of perforations through which fluid exits the cyclone chamber. Fluid within the cyclone chamber is then free to spiral about the shroud and over the inlet opening.Type: GrantFiled: March 8, 2018Date of Patent: August 25, 2020Assignee: Dyson Technology LimitedInventors: James Dyson, Jeremy William Crouch, James Stuart Robertson, Peter David Gammack, Simon Edward Ireland
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Patent number: 10756166Abstract: FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ?MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ?MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.Type: GrantFiled: July 30, 2018Date of Patent: August 25, 2020Assignee: pSemi CorporationInventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
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Patent number: 10699520Abstract: A wagering game system and its operations are described herein. In some embodiments, the operations can include detecting that one or more wearable computers are within a proximity range to a wagering game machine. In some examples, the operations further include determining one or more characteristics associated with the one or more wearable computers in response to the detecting that the one or more wearable computers are within the proximity range to the wagering game machine. In some examples, the operations further include providing a feature associated with a wagering game based on the one or more characteristics of the one or more wearable computers.Type: GrantFiled: November 21, 2018Date of Patent: June 30, 2020Assignee: SG Gaming, Inc.Inventors: Michael R. Bytnar, Michael Vincent Dicillo, Patrick M. Gustafson, Jeremy Michael Hornik, Gary John Oswald, Richard Barry Robbins, Nickey C. Shin, Jesse M. Smith, Simon Edward Sunblade, Jamie W. Vann, Muthu Velu, Matthew J. Ward, Steven J. Zoloto, Dale Robert Buchholz, Mark B. Gagner, Craig Joe Sylla
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Patent number: 10700642Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.Type: GrantFiled: January 4, 2019Date of Patent: June 30, 2020Assignee: pSemi CorporationInventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
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Publication number: 20200176252Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).Type: ApplicationFiled: November 20, 2019Publication date: June 4, 2020Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
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Patent number: 10672726Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.Type: GrantFiled: May 19, 2017Date of Patent: June 2, 2020Assignee: pSemi CorporationInventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
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Publication number: 20200153425Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: ApplicationFiled: November 13, 2019Publication date: May 14, 2020Inventors: Tero Tapio Ranta, Simon Edward Willard
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Patent number: 10629621Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.Type: GrantFiled: January 3, 2019Date of Patent: April 21, 2020Assignee: pSemi CorporationInventor: Simon Edward Willard
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Patent number: 10630280Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: GrantFiled: January 29, 2019Date of Patent: April 21, 2020Assignee: pSemi CorporationInventors: Simon Edward Willard, Tero Tapio Ranta