Patents by Inventor Spyridon Skordas

Spyridon Skordas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240332239
    Abstract: A three-dimensional (3D) die architecture is provided. The 3D die architecture includes a first die and a second die. The second die includes multiple interior layers of various types and is hybrid bonded to the first die along a hybrid bond layer. The 3D die architecture further includes oxide liner material extending from an exposed surface of the second die to the hybrid bond layer, a first through-silicon-via (TSV) extending from the exposed surface to a corresponding one of the multiple interior layers and a second TSV extending within the oxide liner material from the exposed surface to the hybrid bond layer.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Inventors: Nicholas Alexander Polomoff, Mukta Ghate Farooq, Dale Curtis McHerron, Eric Perfecto, Katsuyuki Sakuma, SPYRIDON SKORDAS
  • Publication number: 20240113055
    Abstract: A hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. Each substrate has a die portion and a crackstop structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Nicholas Alexander Polomoff, Eric Perfecto, Katsuyuki Sakuma, Mukta Ghate Farooq, Spyridon Skordas, Sathyanarayanan Raghavan, Michael P. Belyansky
  • Publication number: 20230409692
    Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Spyridon Skordas
  • Patent number: 11790072
    Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 17, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Spyridon Skordas
  • Publication number: 20230268275
    Abstract: A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 24, 2023
    Inventors: Mukta Ghate Farooq, James J. Kelly, Eric Perfecto, SPYRIDON SKORDAS, Dale Curtis McHerron
  • Patent number: 11355379
    Abstract: A method of fabricating a semiconductor structure includes forming a scissionable layer that is able to absorb infrared (IR) radiation, below a first carrier wafer. A first hard-dielectric layer is formed below the scissionable layer. A second hard-dielectric layer is formed on a top surface of a semiconductor wafer. The first dielectric layer is bonded with the second dielectric layer. Connectors on a bottom portion of the semiconductor wafer are formed to provide an electric connection to the semiconductor wafer. A second carrier wafer is connected to the connectors on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer with an IR, by passing the IR through the first carrier wafer. A back end of line (BEOL) wiring passing from a top surface of the semiconductor wafer through the first and second dielectric layers is provided.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 7, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta Ghate Farooq, Dale Curtis McHerron, Spyridon Skordas
  • Publication number: 20220165601
    Abstract: A method of fabricating a semiconductor structure includes forming a scissionable layer that is able to absorb infrared (IR) radiation, below a first carrier wafer. A first hard-dielectric layer is formed below the scissionable layer. A second hard-dielectric layer is formed on a top surface of a semiconductor wafer. The first dielectric layer is bonded with the second dielectric layer. Connectors on a bottom portion of the semiconductor wafer are formed to provide an electric connection to the semiconductor wafer. A second carrier wafer is connected to the connectors on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer with an IR, by passing the IR through the first carrier wafer. A back end of line (BEOL) wiring passing from a top surface of the semiconductor wafer through the first and second dielectric layers is provided.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Mukta Ghate Farooq, Dale Curtis McHerron, Spyridon Skordas
  • Patent number: 11322361
    Abstract: An apparatus that includes a solution bath of a seasoned solution, the seasoned solution containing a mixture of hydrofluoric acid, nitric acid, and acetic acid; and one or more silicon wafers being suspended in a position above the solution bath, wherein at least a portion of the mixture having been used in thinning the one or more silicon wafers.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: Da Song, Allan Ward Upham, Cornelius Brown Peethala, Kevin Winstel, Spyridon Skordas
  • Patent number: 11239167
    Abstract: Copper (Cu)-to-Cu bonding techniques for high bandwidth interconnects on a bridge chip attached to chips which are further attached to a packaging substrate are provided. In one aspect, a method of forming an interconnect structure is provided. The method includes: bonding individual chips to at least one bridge chip via Cu-to-Cu bonding to form a multi-chip structure; and bonding the multi-chip structure to a packaging substrate via solder bonding, after the Cu-to-Cu bonding has been performed, to form the interconnect structure including the individual chips bonded to the at least one bridge chip and to the packaging substrate. A structure formed by the method is also provided.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Mukta Ghate Farooq, Ravi K. Bonam, James J. Kelly, Spyridon Skordas
  • Patent number: 11182722
    Abstract: A method includes monitoring with at least one monitoring tool one or more activities associated with an enterprise. The method further includes analyzing data input from the at least one monitoring tool of the one or more activities, and determining, based on analytics performed on the data input and an implemented policy, when the one or more activities qualifies as an incident. A remedial response responsive to the incident is initiated. The monitoring, analyzing, determining and initiating steps are performed by at least one processing device including a processor operatively coupled to a memory.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alex Richard Hubbard, Spyridon Skordas, Marc A. Bergendahl, Cody John Murray, Gauri Karve, Lawrence A. Clevenger
  • Patent number: 11068896
    Abstract: Devices and methods for granting requests for authorization using data of devices associated with requestors are disclosed. A method includes: receiving, by a computing device, a request for authorization; receiving, by the computing device, identification information for at least one device of a requestor; determining, by the computing device, a risk score using the received identification information for the at least one device of the requestor; and in response to the risk score exceeding a predetermined threshold, the computing device granting the request for authorization.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Spyridon Skordas, Lawrence A. Clevenger, Richard C. Johnson
  • Publication number: 20210175174
    Abstract: Copper (Cu)-to-Cu bonding techniques for high bandwidth interconnects on a bridge chip attached to chips which are further attached to a packaging substrate are provided. In one aspect, a method of forming an interconnect structure is provided. The method includes: bonding individual chips to at least one bridge chip via Cu-to-Cu bonding to form a multi-chip structure; and bonding the multi-chip structure to a packaging substrate via solder bonding, after the Cu-to-Cu bonding has been performed, to form the interconnect structure including the individual chips bonded to the at least one bridge chip and to the packaging substrate. A structure formed by the method is also provided.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 10, 2021
    Inventors: Mukta Ghate Farooq, Ravi K. Bonam, James J. Kelly, Spyridon Skordas
  • Patent number: 10915620
    Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Spyridon Skordas
  • Publication number: 20200302352
    Abstract: A method includes monitoring with at least one monitoring tool one or more activities associated with an enterprise. The method further includes analyzing data input from the at least one monitoring tool of the one or more activities, and determining, based on analytics performed on the data input and an implemented policy, when the one or more activities qualifies as an incident. A remedial response responsive to the incident is initiated. The monitoring, analyzing, determining and initiating steps are performed by at least one processing device including a processor operatively coupled to a memory.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Alex Richard Hubbard, Spyridon Skordas, Marc A. Bergendahl, Cody John Murray, Gauri Karve, Lawrence A. Clevenger
  • Patent number: 10777433
    Abstract: A wafer bonding method includes placing a first wafer on a first bonding framework including a plurality of outlet holes around a periphery of the first bonding framework. A second wafer is placed on a second bonding framework that includes a plurality of inlet holes around a periphery of the second bonding framework. The first bonding framework is in overlapping relation to the second bonding framework such that a gap exist between the first wafer and the second wafer. A gas stream is circulated through the gap between the first wafer and the second wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the first wafer and the second wafer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: September 15, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Wei Lin, Spyridon Skordas, Robert R. Young, Jr.
  • Patent number: 10681207
    Abstract: Communication source identifier verification system mechanisms are provided. The mechanisms receive communication information for a communication initiated between a source communication system and a destination communication system. The communication information comprises a source identifier and a local device identifier signature specifying zero or more local device identifiers of devices local to the source communication system. The mechanisms retrieve valid device identifier information for an authorized communication source corresponding to the identifier of the source communication system. The mechanisms execute a verification operation that verifies whether the source identifier is validly associated with the source communication system based on the retrieved valid device identifier information and the local device identifier signature.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Richard C. Johnson, Spyridon Skordas, Lawrence A. Clevenger
  • Patent number: 10615139
    Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20190371615
    Abstract: An apparatus that includes a solution bath of a seasoned solution, the seasoned solution containing a mixture of hydrofluoric acid, nitric acid, and acetic acid; and one or more silicon wafers being suspended in a position above the solution bath, wherein at least a portion of the mixture having been used in thinning the one or more silicon wafers.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Inventors: Da Song, Allan Ward Upham, Cornelius Brown Peethala, Kevin Winstel, SPYRIDON SKORDAS
  • Publication number: 20190325126
    Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Spyridon Skordas
  • Publication number: 20190325127
    Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Spyridon Skordas