Patents by Inventor Spyridon Skordas

Spyridon Skordas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9671215
    Abstract: Wafer to wafer alignment which includes a first semiconductor wafer and a second semiconductor wafer. The first and second semiconductor wafers have selectively-activated alignment arrays for aligning the first semiconductor wafer with the second semiconductor wafer. Each of the alignment arrays include an alignment structure which includes an antenna connected to a semiconductor device. The antenna in each of the alignment arrays is selectively activated to act as a charge source or as a charge sensing receptor. The alignment arrays are located in the kerf areas of the semiconductor wafers. The semiconductor wafers are aligned when the charge sources on one semiconductor wafer match with the charge sensing receptors on the other semiconductor wafer.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Spyridon Skordas
  • Patent number: 9640514
    Abstract: A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Lin, Troy L. Graves-Abe, Donald F. Canaperi, Spyridon Skordas, Matthew T. Shoudy, Binglin Miao, Raghuveer R. Patlolla, Sanjay C. Mehta
  • Patent number: 9620481
    Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel C. Edelstein, Douglas C. La Tulipe, Jr., Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
  • Publication number: 20170097467
    Abstract: Embodiments are directed to a coupler system having an interposer configured to couple optical signals. The interposer includes at least one optoelectronic component formed on a glass substrate. The interposer further includes at least one waveguide formed on the glass substrate and configured to couple the optical signals to or from the at least one optoelectronic component, wherein the at least one waveguide comprises a waveguide material having grain diameters greater than about one micron and an optical loss less than about one decibel per centimeter of optical propagation.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 6, 2017
    Inventors: Stephen M. Gates, Joyeeta Nag, Jason S. Orcutt, Jean-Olivier Plouchart, Spyridon Skordas
  • Patent number: 9564386
    Abstract: A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Son V. Nguyen, Spyridon Skordas, Tuan A. Vo
  • Patent number: 9553054
    Abstract: Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9543229
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9536853
    Abstract: According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9536809
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20160343564
    Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.
    Type: Application
    Filed: May 21, 2015
    Publication date: November 24, 2016
    Inventors: Richard F. INDYK, Deepika PRIYADARSHINI, Spyridon SKORDAS, Edmund J. SPROGIS, Anthony K. STAMPER, Kevin R. WINSTEL
  • Publication number: 20160322324
    Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Application
    Filed: July 13, 2016
    Publication date: November 3, 2016
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9472710
    Abstract: Embodiments are directed to a coupler system having an interposer configured to couple optical signals. The interposer includes at least one optoelectronic component formed on a glass substrate. The interposer further includes at least one waveguide formed on the glass substrate and configured to couple the optical signals to or from the at least one optoelectronic component, wherein the at least one waveguide comprises a waveguide material having grain diameters greater than about one micron and an optical loss less than about one decibel per centimeter of optical propagation.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen M. Gates, Joyeeta Nag, Jason S. Orcutt, Jean-Olivier Plouchart, Spyridon Skordas
  • Patent number: 9472457
    Abstract: A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Lin, Spyridon Skordas, Tuan A. Vo
  • Patent number: 9466538
    Abstract: A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Spyridon Skordas, Subramanian S Iyer, Donald Francis Canaperi, Shidong Li, Wei Lin
  • Patent number: 9401303
    Abstract: The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: July 26, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kangguo Cheng, Jonathan E. Faltermeier, Mukta G. Farooq, Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9378966
    Abstract: A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1×1019 atoms/cm3; collecting the mixture after reacting with the boron doped portions of the one or more silicon wafers; and adding collected mixture back into the solution container to create the etch solution.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brown C. Peethala, Spyridon Skordas, Da Song, Allan Upham, Kevin R. Winstel
  • Publication number: 20160178344
    Abstract: Wafer to wafer alignment which includes a first semiconductor wafer and a second semiconductor wafer. The first and second semiconductor wafers have selectively-activated alignment arrays for aligning the first semiconductor wafer with the second semiconductor wafer. Each of the alignment arrays include an alignment structure which includes an antenna connected to a semiconductor device. The antenna in each of the alignment arrays is selectively activated to act as a charge source or as a charge sensing receptor. The alignment arrays are located in the kerf areas of the semiconductor wafers. The semiconductor wafers are aligned when the charge sources on one semiconductor wafer match with the charge sensing receptors on the other semiconductor wafer.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Spyridon Skordas
  • Publication number: 20160141263
    Abstract: According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Application
    Filed: November 18, 2014
    Publication date: May 19, 2016
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20160118348
    Abstract: Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 28, 2016
    Inventors: Mukta G. FAROOQ, John A. FITZSIMMONS, Erdem KALTALIOGLU, Wei LIN, Spyridon SKORDAS, Kevin R. WINSTEL
  • Publication number: 20160064307
    Abstract: A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 3, 2016
    Inventors: Wei Lin, Son V. Nguyen, Spyridon Skordas, Tuan A. Vo