Patents by Inventor Spyridon Skordas

Spyridon Skordas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9263366
    Abstract: A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Son V. Nguyen, Spyridon Skordas, Tuan A. Vo
  • Publication number: 20160035616
    Abstract: The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 4, 2016
    Inventors: Kangguo Cheng, Johnathan E. Faltermeier, Mukta G. Farooq, Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20150371927
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Application
    Filed: August 30, 2015
    Publication date: December 24, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, JR., Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9214435
    Abstract: Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: December 15, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mukta G. Farooq, Troy L. Graves-Abe, Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20150357207
    Abstract: An apparatus that includes a solution bath of a seasoned solution, the seasoned solution containing a mixture of hydrofluoric acid, nitric acid, and acetic acid; and one or more silicon wafers being suspended in a position above the solution bath, wherein at least a portion of the mixture having been used in thinning the one or more silicon wafers.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 10, 2015
    Inventors: Brown C. Peethala, Spyridon Skordas, Da Song, Allan Upham, Kevin R. Winstel
  • Publication number: 20150357197
    Abstract: A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1×1019 atoms/cm3; collecting the mixture after reacting with the boron doped portions of the one or more silicon wafers; and adding collected mixture back into the solution container to create the etch solution.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 10, 2015
    Inventors: Brown C. Peethala, Spyridon Skordas, Da Song, Allan Upham, Kevin R. Winstel
  • Publication number: 20150348842
    Abstract: A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process.
    Type: Application
    Filed: August 11, 2015
    Publication date: December 3, 2015
    Inventors: Wei Lin, Spyridon Skordas, Tuan A. Vo
  • Publication number: 20150348868
    Abstract: A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 3, 2015
    Applicant: International Business Machines Corporation
    Inventors: Wei Lin, Son V. Nguyen, Spyridon Skordas, Tuan A. Vo
  • Patent number: 9190303
    Abstract: A bonding layer of a first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters is conditionally varied in accordance with the prediction. The thermal treating of the first and second wafer articles can then be performed with respect to another pair of the first and second wafer articles prior to bonding to one another through their respective bonding layers.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUDRIES INC.
    Inventors: Douglas C. La Tulipe, Jr., Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20150318260
    Abstract: A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.
    Type: Application
    Filed: May 5, 2014
    Publication date: November 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas, Robert R. Young, JR.
  • Patent number: 9171749
    Abstract: A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S.2 LLC
    Inventors: Bing Dang, Sarah H. Knickerbocker, Douglas C. La Tulipe, Jr., Spyridon Skordas, Cornelia K. Tsang, Kevin R. Winstel
  • Publication number: 20150279709
    Abstract: A bonding layer of a first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters is conditionally varied in accordance with the prediction. The thermal treating of the first and second wafer articles can then be performed with respect to another pair of the first and second wafer articles prior to bonding to one another through their respective bonding layers.
    Type: Application
    Filed: May 19, 2015
    Publication date: October 1, 2015
    Inventors: Douglas C. La Tulipe, JR., Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9142488
    Abstract: A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas, Tuan A. Vo
  • Publication number: 20150262976
    Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.
    Type: Application
    Filed: May 19, 2015
    Publication date: September 17, 2015
    Inventors: Daniel C. Edelstein, Douglas C. La Tulipe, Jr., Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
  • Publication number: 20150255417
    Abstract: A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith.
    Type: Application
    Filed: May 20, 2015
    Publication date: September 10, 2015
    Inventors: Mukta G. Farooq, Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9105517
    Abstract: A method for wafer alignment includes forming a first alignment circuit within a first semiconductor wafer; the first alignment circuit is configured to emit an optical signal. Next, the first alignment circuit is activated upon receiving a first activation signal from a wafer bonding tool then the optical signal is sent to a second alignment circuit in a second semiconductor wafer in overlapping relation to the first semiconductor wafer. The second alignment circuit transmits a second activation signal to the wafer bonding tool and consequently the wafer bonding tool initiates an alignment technique between the first and second semiconductor wafers. The alignment technique uses the first and second alignment circuits for optical alignment.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Spyridon Skordas
  • Publication number: 20150221610
    Abstract: Separating bonded wafers. A bonded wafer pair is mounted between first and second bonding chucks having flat chuck faces, the first bonding chuck face including adjustable zones capable of movement relative to each other, at least a component of the relative movement is along an axis that is perpendicular to the flat first bonding chuck face. The adjustable zones of the first face are moved relative to each other in a coordinated manner such that a widening gap is formed between the bonding faces of the wafer pair.
    Type: Application
    Filed: April 14, 2015
    Publication date: August 6, 2015
    Inventors: Wei Lin, Spyridon Skordas, Tuan A. Vo
  • Publication number: 20150187733
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9064937
    Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Douglas C. La Tulipe, Jr., Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
  • Patent number: 9058974
    Abstract: Improving wafer-to-wafer bonding alignment. Determining planar distortions of the bonding surface of a host wafer. Mounting a donor wafer on a bonding chuck by a plurality of fixation points, the bonding chuck including multiple zones capable of movement relative to each other. Distorting the bonding surface of the donor wafer by moving the zones of the bonding chuck relative to each other to cause distortions of the bonding surface of the donor wafer such that the distortions of the donor wafer bonding surface correspond to the determined planar distortions of the host wafer bonding surface.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas, Tuan A. Vo