Patents by Inventor Spyridon Skordas
Spyridon Skordas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9059333Abstract: A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith.Type: GrantFiled: December 4, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel
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Patent number: 9059039Abstract: A bonding layer of the first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters can be conditionally varied in accordance with the prediction. The thermally treating of the first wafer article and the thermally treating of the second wafer article can then be performed with respect to another pair of the first and second wafer articles prior to bonding the another pair of wafer articles to one another through their respective bonding layers.Type: GrantFiled: September 6, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Douglas C. La Tulipe, Jr., Wei Lin, Spyridon Skordas, Kevin R. Winstel
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Publication number: 20150155263Abstract: A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith.Type: ApplicationFiled: December 4, 2013Publication date: June 4, 2015Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel
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Publication number: 20150132924Abstract: A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.Type: ApplicationFiled: November 13, 2013Publication date: May 14, 2015Applicant: International Business Machines CorporationInventors: Bing Dang, Sarah H. Knickerbocker, Douglas C. La Tulipe, JR., Spyridon Skordas, Cornelia K. Tsang, Kevin R. Winstel
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Patent number: 9028628Abstract: Oxide-oxide fusion bonding of wafers that includes performing a van der Waals force bonding process with a chuck having at least a flat central zone and an outer annular zone lower than the central zone, an edge portion of a mounted wafer is biased towards the outer annular zone. The van der Waals bonding wave is disrupted at the outer annular zone, causing an edge gap. A thermocompression bonding process is performed that includes heating the bonded wafers to a temperature sufficient to initiate condensation of silanol groups between the bonding surfaces, reducing the atmospheric pressure to cause degassing from between the wafers, applying a compression force to the wafers with flat chucks so as to substantially eliminate the edge gap, and performing a permanent anneal bonding process.Type: GrantFiled: March 14, 2013Date of Patent: May 12, 2015Assignee: International Business Machines CorporationInventors: Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo
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Publication number: 20150072444Abstract: A bonding layer of the first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters can be conditionally varied in accordance with the prediction. The thermally treating of the first wafer article and the thermally treating of the second wafer article can then be performed with respect to another pair of the first and second wafer articles prior to bonding the another pair of wafer articles to one another through their respective bonding layers.Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Douglas C. La Tulipe, JR., Wei Lin, Spyridon Skordas, Kevin R. Winstel
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Publication number: 20150069421Abstract: A method for wafer alignment includes forming a first alignment circuit within a first semiconductor wafer; the first alignment circuit is configured to emit an optical signal. Next, the first alignment circuit is activated upon receiving a first activation signal from a wafer bonding tool then the optical signal is sent to a second alignment circuit in a second semiconductor wafer in overlapping relation to the first semiconductor wafer. The second alignment circuit transmits a second activation signal to the wafer bonding tool and consequently the wafer bonding tool initiates an alignment technique between the first and second semiconductor wafers. The alignment technique uses the first and second alignment circuits for optical alignment.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Fitzsimmons, Spyridon Skordas
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Publication number: 20150035169Abstract: Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.Type: ApplicationFiled: October 20, 2014Publication date: February 5, 2015Inventors: Mukta G. Farooq, Troy L. Graves-Abe, Spyridon Skordas, Kevin R. Winstel
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Publication number: 20140370624Abstract: A bonding apparatus for 3D integration may include a plurality of infrared microscopes that emit and receive infrared light for imaging, a first bonding chuck that holds a first semiconductor structure, and a second bonding chuck that holds a second semiconductor structure, whereby the second bonding chuck has a plurality of openings that are transparent to the received infrared light. A force pin is coupled to the first bonding chuck for applying a predetermined force to the first semiconductor structure for bonding to the second semiconductor structure. A temperature controller is coupled to the second bonding chuck, whereby the temperature controller applies a predetermined temperature to the second semiconductor structure, such that, prior to the bonding, the first and the second semiconductor structure are de-aligned with respect to each other using the plurality of infrared microscopes and the plurality of openings.Type: ApplicationFiled: June 18, 2013Publication date: December 18, 2014Inventors: Mukta G. Farooq, Spyridon Skordas
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Publication number: 20140356981Abstract: A method for wafer bonding includes measuring grid distortion for a mated pairing of wafers to be bonded to determine if misalignment exists between the wafers. During processing of subsequent wafers, magnification of one or more lithographic patterns is adjusted to account for the misalignment. The subsequent wafers are bonded with reduced misalignment.Type: ApplicationFiled: May 28, 2013Publication date: December 4, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alex R. HUBBARD, Douglas C. LA TULIPE, JR., Spyridon SKORDAS, Kevin R. WINSTEL
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Publication number: 20140356983Abstract: A method generally for improving wafer-to-wafer bonding alignment. Planar distortions of the bonding surface of a host wafer are determined. The bonding surface of a donor wafer is distorted such that the distortions of the donor wafer bonding surface correspond to the determined planar distortions of the host wafer bonding surface. Also, a method to separate bonded wafers. A bonded wafer pair is mounted between first and second bonding chucks having flat chuck faces, the first bonding chuck face including adjustable zones capable of movement relative to each other, at least a component of the relative movement is along an axis that is perpendicular to the flat first bonding chuck face. The adjustable zones of the first face are moved relative to each other in a coordinated manner such that a widening gap is formed between the bonding faces of the wafer pair.Type: ApplicationFiled: June 3, 2013Publication date: December 4, 2014Inventors: Wei Lin, Spyridon Skordas, Tuan A. Vo
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Publication number: 20140353839Abstract: A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process.Type: ApplicationFiled: May 30, 2013Publication date: December 4, 2014Applicant: International Business Machines CorporationInventors: Wei Lin, Spyridon Skordas, Tuan A. Vo
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Publication number: 20140353828Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.Type: ApplicationFiled: May 30, 2013Publication date: December 4, 2014Inventors: Daniel C. Edelstein, Douglas C. La Tulipe, JR., Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
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Patent number: 8900885Abstract: A method for wafer bonding includes measuring grid distortion for a mated pairing of wafers to be bonded to determine if misalignment exists between the wafers. During processing of subsequent wafers, magnification of one or more lithographic patterns is adjusted to account for the misalignment. The subsequent wafers are bonded with reduced misalignment.Type: GrantFiled: May 28, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Alex R. Hubbard, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
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Publication number: 20140265165Abstract: A chuck face of a wafer bonding chuck that includes a flat central zone and an outer annular zone contiguous to the central zone, the outer annular zone being lower than the flat central zone such that an annular edge portion of a wafer that is mounted to the chuck face has a convex profile with respect to the chuck face of the bonding chuck. The outer annular zone may move along an axis that is perpendicular to the central zone. The chuck face may include a plurality of contiguous zones, with at least one of the zones moveable with respect to another of the zones.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wei Lin, Spyridon Skordas, Tuan A. Vo
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Publication number: 20140261960Abstract: Oxide-oxide fusion bonding of wafers that includes performing a van der Waals force bonding process with a chuck having at least a flat central zone and an outer annular zone lower than the central zone, an edge portion of a mounted wafer is biased towards the outer annular zone. The van der Waals bonding wave is disrupted at the outer annular zone, causing an edge gap. A thermocompression bonding process is performed that includes heating the bonded wafers to a temperature sufficient to initiate condensation of silanol groups between the bonding surfaces, reducing the atmospheric pressure to cause degassing from between the wafers, applying a compression force to the wafers with flat chucks so as to substantially eliminate the edge gap, and performing a permanent anneal bonding process.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo
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Patent number: 8765578Abstract: A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.Type: GrantFiled: June 6, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Douglas C. La Tulipe, Jr., Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
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Publication number: 20130328174Abstract: A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.Type: ApplicationFiled: June 6, 2012Publication date: December 12, 2013Applicant: International Business Machines CorporationInventors: Douglas C. La Tulipe, JR., Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
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Publication number: 20130307160Abstract: Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.Type: ApplicationFiled: May 21, 2012Publication date: November 21, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Troy L. Graves-Abe, Spyridon Skordas, Kevin R. Winstel
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Patent number: 8563403Abstract: A method includes forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer; forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer; bonding the first bonding layer of first IC device to the second bonding layer of second IC device; thinning a backside of the first IC device so as to expose the alignment via; and using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.Type: GrantFiled: June 27, 2012Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Spyridon Skordas, Richard P. Volant, Kevin R. Winstel