Abstract: A circuit for detecting power analysis attacks includes at least one load circuit, a power supply line, and a switch coupled to the load circuit and to the power supply line. The switch is configured to enable and disable the at least one load circuit, and a voltage monitor is configured to sample voltage levels of the supply voltage. A detection circuit is coupled to the switch and to the voltage monitor. The detection circuit is configured to generate control signals for enabling and disabling the at least one load circuit, compare a first voltage level sampled when the at least one load circuit is disabled to a second voltage level sampled when the at least one load circuit is enabled, and generate an attack-detection signal in response to a difference between the sampled first voltage level and the sampled second voltage level being greater than a threshold voltage level.

Abstract: An embodiment of a method to characterize a die is disclosed. The embodiment of the method includes measuring a quality metric of the die, and determining, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, where the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die.

Abstract: An embodiment of a method is disclosed for protecting sensitive data from discovery during an operation performed on input data with the sensitive data. This embodiment of the method includes performing the operation on a first quantity of random data with the sensitive data using a circuit arrangement before performing the operation with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the first quantity of the random data, the operation is performed with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the input data, the operation is performed with the sensitive data on a second quantity of random data using the circuit arrangement.

Abstract: An integrated circuit has a first independent power domain having a first power domain bus electrically connected to first functional blocks and a first power pad electrically connected to the first power domain bus and a second independent power domain having a second power domain bus electrically connected to second functional blocks and a second power pad electrically connected to the second power domain bus. A test element is between the first power domain bus and the second power domain bus.

Abstract: A computer-implemented method is described for determining cost in a non-blocking routing network that provides routing functionality using a single level of a plurality of multiplexers in each row of the routing network. The method includes assigning a respective numerical value, represented by bits, to each row of the routing network. A number of bits that differ between the respective numerical values of each pair of rows of the routing network indicates a number of row traversals necessary to traverse from a first row of the pair to a second row of the pair. A signal routing cost is computed from the number of bits that differ between the respective numerical values of the first row and the second row of the routing network. The calculated signal routing cost is provided to a placement module.

Abstract: An embodiment of a method is disclosed for protecting a key from discovery during decryption of a data stream. This embodiment of the method includes decrypting the data stream with the key. Before completing decryption of the data stream, the method checks consistency between a decrypted portion of the data stream and expected data using a circuit arrangement. In response to an inconsistency between the decrypted portion and the expected data, a tampering signal is generated to indicate tampering is suspected.

Abstract: In one embodiment, a circuit arrangement for performing cryptographic operations is provided. The circuit includes a substitution block, a cryptographic circuit coupled to the substitution block, and a balancing circuit coupled to the substitution block. The substitution block includes a memory unit storing substitution values and ones-complement values that are corresponding ones-complements of the substitution values. The substitution block, responsive to a request to read a specified one of the substitution values, concurrently reads and outputs the specified substitution value and the corresponding ones-complement value. A power consumed in reading the specified substitution value is uniform with a power consumed in reading another one of the substitution values. The cryptographic circuit and the balancing circuit are configured to concurrently operate on each substitution value and the corresponding ones-complement value read from the memory, respectively.

Abstract: A method of providing non-volatile memory in an integrated circuit is disclosed. The method may comprise storing a plurality of data blocks in volatile memory elements of the integrated circuit, wherein each data block of the plurality of data blocks comprises a plurality of data bits; reading back the plurality of data bits associated with a data block of the plurality of data blocks; determining, by a control circuit, whether values read back for the plurality of data bits associated with the data block indicate valid data in the data block; and reading back, for another data block of the plurality of data blocks, stored data bits to determine a value for the other data block. A circuit for providing non-volatile memory in an integrated circuit is also disclosed.

Abstract: In one embodiment of the invention, a method is provided for protecting against attacks on security of a programmable integrated circuit (IC). At least a portion of an encrypted bitstream input to the programmable IC is decrypted with a cryptographic key stored in the programmable IC. A number of failures to decrypt the encrypted bitstream is tracked. The tracked number is stored in a memory of the programmable IC that retains the number across on-off power cycles of the programmable IC. In response to the number of failures exceeding a threshold, data that prevents the decryption key from being used for a subsequent decryption of a bitstream is stored in the programmable IC.

Abstract: A programmable interconnect element for an integrated circuit device is described. The programmable interconnect comprises a first selection circuit coupled to a plurality of input lines and having a first output; a register having a first input coupled to the first output; and a second selection circuit enabling the selection of a value at the first output or a value stored by the register. A method of implementing a programmable interconnect element is also disclosed.

Abstract: A method of correcting adjacent bit errors in a memory is disclosed. The method comprises determining that there are errors in each set of two non-overlapping sets of the memory; changing a stored value of a memory cell of the memory until it is determined that a single error exists in the memory; identifying a location of the single error in the memory; and correcting the single error in the memory. A circuit for detecting adjacent bit errors in a memory having alternating even memory cells and odd memory cells is also disclosed.

Abstract: In one embodiment, a method is provided for analyzing a circuit design. For each sub-circuit of a plurality of sub-circuits specified in the circuit design, a logic level probability is determined for each output of the sub-circuit. The logic level probability indicates the probability that an output of the sub-circuit will have a first value in response to possible values of inputs to the sub-circuit. Each logic level probability is converted to a switching probability that indicates a probability that a switching event will occur at the respective output of the sub-circuit within a time period. The switching probability is stored in a memory.

Abstract: A multiplexer-based network provides the routing equivalent to a non-blocking crossbar network having a plurality of crossbar switches making up an ingress, middle, and egress stages. The non-blocking crossbar network includes crossbar rows, each including outbound and inbound internal connections to another crossbar row. The multiplexer-based network includes multiplexer-based network rows. Each multiplexer-based network row corresponds to a crossbar row of the crossbar network and includes at least one global input, at least one global output, internal inputs, internal outputs, and a corresponding set of multiplexers. Each set of multiplexers includes an internal multiplexer for each respective outbound internal connection of the respective crossbar row. The internal multiplexer includes inputs for signals routable to the respective outbound internal connection. At least one global multiplexer provides a signal to a global output of the multiplexer-based network row.

Abstract: In one aspect, a method for providing encrypted information includes encrypting a true message to form an encrypted true message. A ciphertext message including the encrypted true message is formed, where multiple messages are decryptable from the ciphertext message. The messages include a true message including true information and at least one decoy message including false information.

Abstract: A nano-electric switch includes a cavity base, a confinement wall, and a cavity top defining a cavity. A floating conductive bridge movable within the cavity completes an electrical circuit between a first electrical contact and a second electrical contact in a first selectable position, and breaks the electrical circuit in a second selectable position.

Abstract: A method of using an integrated circuit (IC) can include reading a device code from a selected IC, calculating a measure of randomness from a plurality of values specified within the device code, and comparing the measure of randomness to a randomness criterion. A determination can be made as to whether the selected IC is compromised according to the comparison. An intellectual property (IP) protection method can include determining a list of controlled IP cores within a bitstream specifying a circuit design, creating a bitstream identifier within the bitstream that is associated with the list of controlled IP cores, and determining a count specifying a number of integrated circuits loaded with the bitstream.

Abstract: A non-blocking routing network includes a plurality of external inputs and external outputs. Each row of a first plurality of routing rows provides a routing path from at least one of the external inputs to at least one of the external outputs and includes first through fourth multiplexers. Each row of a second plurality of routing rows provides a routing path from at least two of the external inputs to at least two of the external outputs. Each routing row of the second plurality of routing rows contains at least one less multiplexer relative to a routing row of the first plurality of routing rows, the one less multiplexer corresponding to at least two external inputs or two external outputs that are logically equivalent to one another.

Abstract: An integrated circuit includes a fingerprint element and a decryption circuit. The fingerprint element generates a fingerprint, where the fingerprint is reproducible and represents an inherent manufacturing process characteristic unique to the integrated circuit device. The decryption circuit decrypts, using a decryption key that is based on the fingerprint, an encrypted data in order to extract data. In one embodiment, the propagation delay of various circuit elements are used to generate the fingerprint. In another embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In yet another embodiment, a ratio of measurable values is used to generate the fingerprint. In another embodiment, differences in transistor threshold voltages are used to generate the fingerprint. In yet another embodiment, variations in line widths are used to generate the fingerprint.

Abstract: An embodiment of the invention relates to an integrated circuit that includes an identifier reader which may be, e.g., a physically unclonable function reader that generates a unique and reproducible identifier for the integrated circuit, and a related method. An error correction code may be employed to correct an error in the value of the reproducible identifier. Values of signals in the integrated circuit are selectively inverted dependent on values of the reproducible identifier, and an error corrector uses the values of the reproducible identifier to restore the values of the signals. The signals may be produced as outputs of look-up tables that selectively invert the values of the signals dependent on the value of the reproducible identifier. The signals may be inputs to the integrated circuit, internal signals, outputs, or state data. A test may validate a state of the integrated circuit and disable operation if the test fails.

Abstract: Various methods for inhibiting reverse engineering of a circuit design are provided. In one embodiment, a circuit design is initially mapped to a plurality of identified hardware components of a target device using a first table that indicates a first set of logic patterns that hardware components of the target device can implement. Unused hardware components are identified, and at least one logic pattern of the circuit design is remapped to one of the unused hardware components using a second mapping table. The second table indicates a second set of logic patterns, not indicated by the first mapping table, that one of the unused hardware components is configurable to implement.