Patents by Inventor Stephen M. Trimberger

Stephen M. Trimberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8493090
    Abstract: A multiplexer-based network provides the routing equivalent to a non-blocking crossbar network having a plurality of crossbar switches making up an ingress, middle, and egress stages. The non-blocking crossbar network includes crossbar rows, each including outbound and inbound internal connections to another crossbar row. The multiplexer-based network includes multiplexer-based network rows. Each multiplexer-based network row corresponds to a crossbar row of the crossbar network and includes at least one global input, at least one global output, internal inputs, internal outputs, and a corresponding set of multiplexers. Each set of multiplexers includes an internal multiplexer for each respective outbound internal connection of the respective crossbar row. The internal multiplexer includes inputs for signals routable to the respective outbound internal connection. At least one global multiplexer provides a signal to a global output of the multiplexer-based network row.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: July 23, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8472619
    Abstract: In one aspect, a method for providing encrypted information includes encrypting a true message to form an encrypted true message. A ciphertext message including the encrypted true message is formed, where multiple messages are decryptable from the ciphertext message. The messages include a true message including true information and at least one decoy message including false information.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: June 25, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8441038
    Abstract: A nano-electric switch includes a cavity base, a confinement wall, and a cavity top defining a cavity. A floating conductive bridge movable within the cavity completes an electrical circuit between a first electrical contact and a second electrical contact in a first selectable position, and breaks the electrical circuit in a second selectable position.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: May 14, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8427193
    Abstract: A method of using an integrated circuit (IC) can include reading a device code from a selected IC, calculating a measure of randomness from a plurality of values specified within the device code, and comparing the measure of randomness to a randomness criterion. A determination can be made as to whether the selected IC is compromised according to the comparison. An intellectual property (IP) protection method can include determining a list of controlled IP cores within a bitstream specifying a circuit design, creating a bitstream identifier within the bitstream that is associated with the list of controlled IP cores, and determining a count specifying a number of integrated circuits loaded with the bitstream.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 23, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8415976
    Abstract: A non-blocking routing network includes a plurality of external inputs and external outputs. Each row of a first plurality of routing rows provides a routing path from at least one of the external inputs to at least one of the external outputs and includes first through fourth multiplexers. Each row of a second plurality of routing rows provides a routing path from at least two of the external inputs to at least two of the external outputs. Each routing row of the second plurality of routing rows contains at least one less multiplexer relative to a routing row of the first plurality of routing rows, the one less multiplexer corresponding to at least two external inputs or two external outputs that are logically equivalent to one another.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: April 9, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8418006
    Abstract: An embodiment of the invention relates to an integrated circuit that includes an identifier reader which may be, e.g., a physically unclonable function reader that generates a unique and reproducible identifier for the integrated circuit, and a related method. An error correction code may be employed to correct an error in the value of the reproducible identifier. Values of signals in the integrated circuit are selectively inverted dependent on values of the reproducible identifier, and an error corrector uses the values of the reproducible identifier to restore the values of the signals. The signals may be produced as outputs of look-up tables that selectively invert the values of the signals dependent on the value of the reproducible identifier. The signals may be inputs to the integrated circuit, internal signals, outputs, or state data. A test may validate a state of the integrated circuit and disable operation if the test fails.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 9, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8416950
    Abstract: An integrated circuit includes a fingerprint element and a decryption circuit. The fingerprint element generates a fingerprint, where the fingerprint is reproducible and represents an inherent manufacturing process characteristic unique to the integrated circuit device. The decryption circuit decrypts, using a decryption key that is based on the fingerprint, an encrypted data in order to extract data. In one embodiment, the propagation delay of various circuit elements are used to generate the fingerprint. In another embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In yet another embodiment, a ratio of measurable values is used to generate the fingerprint. In another embodiment, differences in transistor threshold voltages are used to generate the fingerprint. In yet another embodiment, variations in line widths are used to generate the fingerprint.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: April 9, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8418096
    Abstract: Various methods for inhibiting reverse engineering of a circuit design are provided. In one embodiment, a circuit design is initially mapped to a plurality of identified hardware components of a target device using a first table that indicates a first set of logic patterns that hardware components of the target device can implement. Unused hardware components are identified, and at least one logic pattern of the circuit design is remapped to one of the unused hardware components using a second mapping table. The second table indicates a second set of logic patterns, not indicated by the first mapping table, that one of the unused hardware components is configurable to implement.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 9, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8386990
    Abstract: An embodiment of the invention relates to an integrated circuit such as an FPGA wherein a stable unique identifier is produced by reading an intrinsic characteristic of the IC such as a physically unclonable function, and a related method. In one embodiment, a first unique identifier is generated using the intrinsic characteristic and is subdivided into a plurality of first subsets. A second unique identifier is received and subdivided into a plurality of second subsets. The first and second subsets are compared to identify matching subsets to generate the stable unique identifier. Each of the one or more matching subsets includes a particular one of the plurality of first subsets that matches a corresponding one of the plurality of second subsets. The stable unique identifier can be integrated into logic of the IC. Prior to comparing the subsets, the first and second subsets can be transformed with one-way functions.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: February 26, 2013
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Austin H. Lesea
  • Patent number: 8379850
    Abstract: In one embodiment, a cryptographic device is provided. The cryptographic device includes a persistent memory and a decryption control circuit coupled to the persistent memory. The decryption control circuit is configured to receive an encrypted data stream and decrypt a first portion of the encrypted data stream using a first cryptographic key stored in the persistent memory, the first portion including a second cryptographic key. The decryption circuit is configured to decrypt a second portion of the encrypted data stream using the second cryptographic key, the second portion of the encrypted data stream including payload data.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: February 19, 2013
    Assignee: Xilinx, Inc.
    Inventors: Brendan K. Bridgford, Stephen M. Trimberger, Jason J. Moore, Edward S. Peterson, James Wesselkamper, John C. Hoffman
  • Patent number: 8359447
    Abstract: A method and system of detecting data imprinting in a memory is described. Data having known bit values is stored in a location in the memory and the data is read to determine the amount of the known bit values that can be successfully read after an attempt to erase the data. The amount of data that can be successfully read is compare to a threshold. Data bit values of a payload data are inverted to reverse the effects of data imprinting in response to the determined amount exceeding the threshold.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: January 22, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8355502
    Abstract: A security circuit for a reprogrammable logic IC includes an evolved circuit that ties the performance of the security circuit to the physical properties of that particular reprogrammable logic IC. The security circuit can be a decryption and/or encryption circuit that decrypts and/or encrypts, respectively, a configuration bitstream for the IC. Because of the link between the performance of the security circuit and the physical properties of the IC, the security circuit cannot be used in other ICs. For example, an encrypted bitstream that can be decrypted by the security circuit in a first IC will typically not be decrypted by the same security circuit in a second IC, since the physical properties of the two ICs will typically be different. The evolved circuit can comprise a portion of the security circuit, such as a security key generator, or it can comprise the full security circuit.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: January 15, 2013
    Assignee: Xilinx, Inc.
    Inventors: Adam P. Donlin, Stephen M. Trimberger
  • Patent number: 8296604
    Abstract: A method and circuit for providing temporal redundancy for a hardware circuit implemented in an integrated circuit is disclosed. The method comprises implementing a comparison circuit for comparing values in the integrated circuit; coupling an input signal to the hardware circuit; detecting an output signal of the hardware circuit at a first time, wherein the output signal is based upon the input signal; holding the input signal until at least a second time; detecting the output signal of the hardware circuit at the second time; determining, by the comparison circuit, whether the output signal of the hardware circuit at the first time corresponds to the output signal of the hardware circuit at the second time; and generating an error signal based upon determining whether the output signal of the hardware circuit at the first time corresponds to the output signal of the hardware circuit at the second time.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: October 23, 2012
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8242805
    Abstract: In one embodiment, a method for restricting use of an integrated circuit (IC) is provided. A write-once memory of a programmable IC contains a first die-specific performance grade indicator. In response to receiving an input code having a second die-specific performance grade indicator with a value indicating a level of performance greater than or equal to a level of performance indicated by the first die-specific performance grade indicator, enabling operation of the IC. In response to receiving a configuration bitstream having the second die-specific performance grade indicator with a value indicating a level of performance less than a level of performance indicated by the first die-specific performance grade indicator, preventing operation of the IC.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: August 14, 2012
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8183881
    Abstract: Method and apparatus for using configuration memory for buffer memory is described. Drivers associated with a portion of the configuration memory are rendered incapable of creating a contentious state irrespective of information stored the portion of configuration memory. Configuration data is received in a non-configuration data format and buffered in the portion of the configuration memory.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: May 22, 2012
    Assignee: Xilinx, Inc.
    Inventors: Benjamin J. Stassart, Stephen M. Trimberger
  • Patent number: 8179159
    Abstract: A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: May 15, 2012
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Arifur Rahman
  • Patent number: 8176461
    Abstract: A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing specification contains timing delays of elements located in at least first and second regions of the target device. A circuit design is placed and routed. With a programmed processor, the timing delay of the first timing specification is increased for one or more elements implementing the circuit design in the first region to produce a second timing specification, and a second timing yield of target device is determined from the second timing specification. In response to the second timing yield being larger than a target timing yield, the programmed processor decreases the timing delay of the second timing specification for one or more elements in the second region to compensate for a difference between the second timing yield and the target timing yield to produce a design-specific timing specification.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: May 8, 2012
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8166366
    Abstract: Partial configuration of programmable circuitry with validation for an integrated circuit is described. An integrated circuit with programmable circuitry is obtained. The programmable circuitry is configured with a first bitstream in a non-dynamic mode of operation, after which the integrated circuit includes a configuration controller coupled to a buffer, an internal configuration access port, and an error checker. A portion of a second bitstream is loaded into the buffer for a dynamic partial configuration mode of operation. The portion of the second bitstream loaded into the buffer is validated with the error checker as being acceptable, after which the portion of the second bitstream is instantiated in the programmable circuitry via the internal configuration access port.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: April 24, 2012
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Brendan K. Bridgford
  • Patent number: 8155907
    Abstract: Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: April 10, 2012
    Assignee: Xilinx, Inc.
    Inventors: Austin H. Lesea, Stephen M. Trimberger, Christopher H. Kingsley, Satyaki Das, Tim Tuan
  • Publication number: 20120060037
    Abstract: An embodiment of a method is disclosed for protecting a key from discovery during decryption of a data stream. This embodiment of the method includes decrypting the data stream with the key. Before completing decryption of the data stream, the method checks consistency between a decrypted portion of the data stream and expected data using a circuit arrangement. In response to an inconsistency between the decrypted portion and the expected data, a tampering signal is generated to indicate tampering is suspected.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 8, 2012
    Applicant: XILINX, INC.
    Inventor: Stephen M. Trimberger