Patents by Inventor Stephen M. Trimberger

Stephen M. Trimberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8296604
    Abstract: A method and circuit for providing temporal redundancy for a hardware circuit implemented in an integrated circuit is disclosed. The method comprises implementing a comparison circuit for comparing values in the integrated circuit; coupling an input signal to the hardware circuit; detecting an output signal of the hardware circuit at a first time, wherein the output signal is based upon the input signal; holding the input signal until at least a second time; detecting the output signal of the hardware circuit at the second time; determining, by the comparison circuit, whether the output signal of the hardware circuit at the first time corresponds to the output signal of the hardware circuit at the second time; and generating an error signal based upon determining whether the output signal of the hardware circuit at the first time corresponds to the output signal of the hardware circuit at the second time.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: October 23, 2012
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8242805
    Abstract: In one embodiment, a method for restricting use of an integrated circuit (IC) is provided. A write-once memory of a programmable IC contains a first die-specific performance grade indicator. In response to receiving an input code having a second die-specific performance grade indicator with a value indicating a level of performance greater than or equal to a level of performance indicated by the first die-specific performance grade indicator, enabling operation of the IC. In response to receiving a configuration bitstream having the second die-specific performance grade indicator with a value indicating a level of performance less than a level of performance indicated by the first die-specific performance grade indicator, preventing operation of the IC.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: August 14, 2012
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8183881
    Abstract: Method and apparatus for using configuration memory for buffer memory is described. Drivers associated with a portion of the configuration memory are rendered incapable of creating a contentious state irrespective of information stored the portion of configuration memory. Configuration data is received in a non-configuration data format and buffered in the portion of the configuration memory.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: May 22, 2012
    Assignee: Xilinx, Inc.
    Inventors: Benjamin J. Stassart, Stephen M. Trimberger
  • Patent number: 8179159
    Abstract: A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: May 15, 2012
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Arifur Rahman
  • Patent number: 8176461
    Abstract: A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing specification contains timing delays of elements located in at least first and second regions of the target device. A circuit design is placed and routed. With a programmed processor, the timing delay of the first timing specification is increased for one or more elements implementing the circuit design in the first region to produce a second timing specification, and a second timing yield of target device is determined from the second timing specification. In response to the second timing yield being larger than a target timing yield, the programmed processor decreases the timing delay of the second timing specification for one or more elements in the second region to compensate for a difference between the second timing yield and the target timing yield to produce a design-specific timing specification.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: May 8, 2012
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8166366
    Abstract: Partial configuration of programmable circuitry with validation for an integrated circuit is described. An integrated circuit with programmable circuitry is obtained. The programmable circuitry is configured with a first bitstream in a non-dynamic mode of operation, after which the integrated circuit includes a configuration controller coupled to a buffer, an internal configuration access port, and an error checker. A portion of a second bitstream is loaded into the buffer for a dynamic partial configuration mode of operation. The portion of the second bitstream loaded into the buffer is validated with the error checker as being acceptable, after which the portion of the second bitstream is instantiated in the programmable circuitry via the internal configuration access port.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: April 24, 2012
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Brendan K. Bridgford
  • Patent number: 8155907
    Abstract: Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: April 10, 2012
    Assignee: Xilinx, Inc.
    Inventors: Austin H. Lesea, Stephen M. Trimberger, Christopher H. Kingsley, Satyaki Das, Tim Tuan
  • Publication number: 20120060037
    Abstract: An embodiment of a method is disclosed for protecting a key from discovery during decryption of a data stream. This embodiment of the method includes decrypting the data stream with the key. Before completing decryption of the data stream, the method checks consistency between a decrypted portion of the data stream and expected data using a circuit arrangement. In response to an inconsistency between the decrypted portion and the expected data, a tampering signal is generated to indicate tampering is suspected.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 8, 2012
    Applicant: XILINX, INC.
    Inventor: Stephen M. Trimberger
  • Publication number: 20120060038
    Abstract: An embodiment of a method is disclosed for protecting sensitive data from discovery during an operation performed on input data with the sensitive data. This embodiment of the method includes performing the operation on a first quantity of random data with the sensitive data using a circuit arrangement before performing the operation with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the first quantity of the random data, the operation is performed with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the input data, the operation is performed with the sensitive data on a second quantity of random data using the circuit arrangement.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 8, 2012
    Applicant: XILINX, INC.
    Inventor: Stephen M. Trimberger
  • Patent number: 8117580
    Abstract: Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device. Test bitstreams associated with the user bitstreams are optionally also included in the memory device. Under the control of a configuration control circuit, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the configuration procedure terminates.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: February 14, 2012
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8104012
    Abstract: Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.
    Type: Grant
    Filed: January 31, 2009
    Date of Patent: January 24, 2012
    Assignee: Xilinx, Inc.
    Inventors: Matthew H. Klein, Edward S. McGettigan, Stephen M. Trimberger, James M. Simkins, Brian D. Philofsky, Subodh Gupta
  • Patent number: 8098081
    Abstract: A method is implemented for generating a non-blocking routing network design from a crossbar switch-based network design. The non-blocking routing network design includes connections to logic blocks of a programmable integrated circuit. A programmed processor is used to determine, for each row of the crossbar switch-based network design, switches in the row that provide switching functions for logically equivalent external connections, the external connections being one of external inputs and external outputs. The identified switches are removed from the crossbar switched-based network design. Information about the identified switches and the logically equivalent external connections is then stored for access by a placement module associated with the programmable integrated circuit.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: January 17, 2012
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8058707
    Abstract: Semiconductor devices having redundant through-die vias (TDVs) and methods of fabricating the same are described. A substrate is provided having conductive interconnect formed on an active side thereof. Through die vias (TDVs) are formed in the substrate between a backside and the active side thereof. The TDVs include signal TDVs, redundant TDVs (i.e., redundant signal TDVs), and power supply TDVs. The signal TDVs are spaced apart from the redundant TDVs to form a pattern of TDV pairs. The power supply TDVs are interspersed among the TDV pairs. The conductive interconnect includes first signal conductors electrically coupling each of the signal TDVs to a respective one of the redundant TDVs defining a respective one of the TDV pairs.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: November 15, 2011
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Arifur Rahman
  • Publication number: 20110252244
    Abstract: In one embodiment of the present invention, a secure cryptographic circuit arrangement is provided. The secure cryptographic circuit includes a cryptographic processing block, a spreading sequence generator, and a delay control circuit. The cryptographic processing block has a plurality of signal paths. One or more of the plurality of signal paths includes respective adjustable delay circuits. The spreading sequence generator is configured to output a sequence of pseudo-random numbers. The delay control circuit has an input coupled to an output of the spreading sequence number generator and one or more outputs coupled to respective delay adjustment inputs of the adjustable delay circuits. The delay control circuit is configured to adjust the adjustable delay circuits based on the pseudo-random numbers.
    Type: Application
    Filed: April 7, 2010
    Publication date: October 13, 2011
    Applicant: Xilinx, Inc.
    Inventors: Austin H. Lesea, Stephen M. Trimberger
  • Patent number: 8024688
    Abstract: A method for detecting reverse engineering of a configuration bitstream for an integrated circuit is described. A user design is obtained. It is determined if the user design is a degenerate design. If the user design is a degenerate design, it is determined if a trip point for bitstream generation has been tripped. If the trip point for the bitstream generation has not been tripped, deterrence information is updated and the bitstream generation is allowed to take place. If the trip point for the bitstream generation has been tripped, at least one reverse engineering countermeasure is initiated.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: September 20, 2011
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7991712
    Abstract: An evolution approach involves the automatic generation of an evaluation function. According to an example embodiment of the present invention, a consensus result from a population of designs is used to evaluate designs in the population for fitness. New designs are evolved using the consensus result as an evaluation function, with newly-evolved designs replacing ones of the population of designs determined to be unfit. With this approach, automatic design evolution is carried out independently from a fixed evaluation function, which is sometimes susceptible to error.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: August 2, 2011
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7982497
    Abstract: The logical functionality of a non-blocking multiplexer-based network is equivalent to a crossbar network with an ingress stage, a middle stage and an egress stage. Crossbar rows of the crossbar network include both outbound and inbound internal connections between other crossbar rows. The multiplexer-based network has corresponding rows and connections. The multiplexer-based network includes rows with an internal multiplexer for each respective outbound internal connection of a corresponding crossbar row. The internal multiplexer includes inputs for signals routable to the respective outbound internal connection. At least one global multiplexer provides a signal selected from a set of inputs that includes each input of the respective crossbar row.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: July 19, 2011
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7979826
    Abstract: Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code is applied to configuration data. Thus, the higher overhead required for a Hamming code applies to only a few words in the bitstream. The instructions are corrected on receipt of the word that includes the Hamming code, so the instructions are executed correctly even if a transmission error has occurred. However, configuration data can be stored in the configuration memory without correction. With a product code, the exact location of an erroneous bit is not known until the end of the transmission, when a parity word is received. At this time, the PLD can go back and correct erroneous bits in the configuration data prior to enabling the newly loaded design.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: July 12, 2011
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7979827
    Abstract: A method of configuring a device having programmable logic is disclosed. The method comprises generating a netlist associated with a circuit design; coupling the netlist to the device having programmable logic; performing a re-targeting function using a circuit on the device having programmable logic; generating configuration bits for configuring the programmable logic; and configuring the programmable logic to implement the circuit design according to the configuration bits based upon the netlist and results of the re-targeting function.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: July 12, 2011
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Austin H. Lesea
  • Patent number: 7973555
    Abstract: A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: July 5, 2011
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Arifur Rahman