Patents by Inventor Steven Bentley

Steven Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190326286
    Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.
    Type: Application
    Filed: April 20, 2018
    Publication date: October 24, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Soss, Steven Bentley, Daniel Chanemougame, Julien Frougier, Bipul Paul, Lars Liebmann
  • Patent number: 10446451
    Abstract: The present disclosure is directed to various embodiments of a method for forming replacement gate structures for vertical transistors.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Soss, Steven Bentley
  • Patent number: 10446659
    Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Rohit Galatage, Puneet Harischandra Suvarna
  • Publication number: 20190312116
    Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Inventors: Emilie Bourjot, Daniel Chanemougame, Steven Bentley
  • Publication number: 20190279990
    Abstract: Structures for a bitcell of a two-port static random access memory (SRAM) and methods for forming a structure for a bitcell of a two-port SRAM. A storage element of the SRAM includes a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a fin, a first pull-down (PD) VTFET with a fin that is aligned in a first row with the fin of the first PU VTFET, a second PU VTFET with a fin, and a second PD VTFET with a fin that is aligned in a second row with the fin of the second PU VTFET. The structure further includes a read port coupled with the storage element. The read port includes a read port pull-down (RPD) VTFET with a fin and a read port access (RPG) VTFET with a fin that is aligned in a third row with the fin of the RPG VTFET.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: Bipul C. Paul, Joseph Versaggi, Steven Bentley
  • Publication number: 20190259857
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Application
    Filed: December 20, 2018
    Publication date: August 22, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • Publication number: 20190259856
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Application
    Filed: February 16, 2018
    Publication date: August 22, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • Publication number: 20190259858
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Application
    Filed: December 20, 2018
    Publication date: August 22, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • Patent number: 10388760
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • Publication number: 20190252267
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Publication number: 20190214484
    Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Inventors: Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Junli Wang, Muthumanickam Sankarapandian
  • Patent number: 10332969
    Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Patent number: 10312154
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Publication number: 20190148494
    Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, John H. Zhang, Steven Bentley, Hui Zang
  • Patent number: 10283621
    Abstract: Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Hui Zang, Steven Bentley
  • Patent number: 10269812
    Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, John H. Zhang, Steven Bentley, Hui Zang
  • Publication number: 20190115444
    Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Steven BENTLEY, Rohit GALATAGE, Puneet Harischandra Suvarna
  • Publication number: 20190115437
    Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 18, 2019
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Patent number: 10256158
    Abstract: Integrated circuit structures include isolation elements extending into a substrate, and source/drain regions of a first transistor contacting the isolation elements. The isolation elements extend from the substrate to the source/drain regions of the first transistor. Isolation layers contact the source/drain regions of the first transistor, and source/drain regions of a second transistor also contact the isolation layers. Thus, the isolation layers are between the source/drain regions of the first transistor and the source/drain regions of the second transistor. Channel regions of the first transistor contact and extend between the source/drain regions of the first transistor, and channel regions of the second transistor contact and extend between the source/drain regions of the second transistor. A gate conductor surrounds sides of the channel region of the first transistor and the channel region of the second transistor.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Puneet H. Suvarna
  • Patent number: 10249710
    Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Deepak Nayak