Patents by Inventor Steven Bentley

Steven Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150325436
    Abstract: Semiconductor devices including a fin and method of forming the semiconductor devices are provided herein. In an embodiment, a method of forming a semiconductor device includes forming a fin overlying a semiconductor substrate. The fin is formed by epitaxially-growing a semiconductor material over the semiconductor substrate, and the fin has a first portion that is proximal to the semiconductor substrate and a second portion that is spaced from the semiconductor substrate by the first portion. A gate structure is formed over the fin and the semiconductor substrate. The first portion of the fin is etched to form a gap between the second portion and the semiconductor substrate.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Steven Bentley, Ajey P. Jacob
  • Patent number: 9178036
    Abstract: One illustrative method disclosed herein includes, among other things, performing at least one recess etching process such that a first portion of a high-k oxide gate insulation layer and a first portion of a metal oxide layer is positioned entirely within a first gate cavity and a second portion of the high-k oxide gate insulation layer, a conformal patterned masking layer and a second portion of the metal oxide layer is positioned entirely within a second gate cavity, performing at least one heating process to form a composite metal-high-k oxide alloy gate insulation layer in the first gate cavity, while preventing metal from the metal oxide material from being driven into the second portion of the high-k oxide gate insulation layer in the second gate cavity during the at least one heating process, and forming gate electrode structures in the gate cavities.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Naim Moumen, Chanro Park, Hoon Kim, Steven Bentley
  • Publication number: 20150303249
    Abstract: Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 22, 2015
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Steven Bentley, Kejia Wang, Sylvie Mignot, Shurong Liang
  • Patent number: 9165837
    Abstract: Methods of forming a defect free heteroepitaxial replacement fin by annealing the sacrificial Si fin with H2 prior to STI formation are provided. Embodiments include forming a Si fin on a substrate; annealing the Si fin with H2; forming a STI layer around the annealed Si fin; annealing the STI layer; removing a portion of the annealed Si fin by etching, forming a recess; forming a replacement fin in the recess; and recessing the annealed STI layer to expose an active replacement fin.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jody Fronheiser, Murat Kerem Akarvardar, Ajey P. Jacob, Steven Bentley
  • Publication number: 20150214369
    Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a <100> crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jody A. Fronheiser, Bharat V. Krishnan, Murat Kerem Akarvardar, Steven Bentley, Ajey Poovannummoottil Jacob, Jinping Liu
  • Publication number: 20150140761
    Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.
    Type: Application
    Filed: January 19, 2015
    Publication date: May 21, 2015
    Applicants: GLOBALFOUNDRIES INC., International Business Machines Corporation, Renesas Electronics Corporation
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Steven Bentley, Toshiharu Nagumo, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz
  • Publication number: 20140217467
    Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Bartlomiej Jan Pawlak, Steven Bentley, Ajey Jacob
  • Patent number: 8716156
    Abstract: One illustrative method disclosed herein includes forming a mandrel structure above a semiconductor substrate, performing an oxidation process to oxidize at least a portion of the mandrel structure so as to thereby define oxidized regions on the mandrel structure, removing the oxidized regions to thereby defined a reduced thickness mandrel structure, forming a plurality of fins on the reduced thickness mandrel structure and performing an etching process to selectively remove at least a portion of the reduced thickness mandrel structure so as to thereby expose at least a portion of each of the fins.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bartlomiej Jan Pawlak, Steven Bentley, Ajey Jacob
  • Publication number: 20060119962
    Abstract: Data reliability testing for a magnetic tape drive is conducted separately for the channels of a magnetic tape drive which write and read tracks of a multiple track magnetic tape. Memory stores testing data representing data separately written to tracks of a multiple track magnetic tape; each of a plurality of read channels reads data sensed by a tape head from a separate track of a magnetic tape; and error processing logic detects differences between data from each of a plurality of the read channels, and stored testing data of the memory representing data written to the same separate tracks.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Inventors: Steven Bentley, Robert Hutchins, Demura Masayuki, Shuhei Nadehara