Patents by Inventor Steven Bentley

Steven Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9966456
    Abstract: One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chanro Park, Steven Bentley, Hoon Kim, Min Gyu Sung, Ruilong Xie
  • Patent number: 9960086
    Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mira Park, Kwan-Yong Lim, Steven Bentley, Amitabh Jain
  • Patent number: 9947804
    Abstract: An IC structure according to the disclosure includes: a substrate; a pair of transistor sites positioned on the substrate, wherein an upper surface of the substrate laterally between the pair of transistor sites defines a separation region; a pair of nanosheet stacks, each positioned on one of the pair of transistor sites; an insulative liner conformally positioned on the upper surface of the substrate within the separation region, and a sidewall surface of each of the pair of transistor sites; a semiconductor mandrel positioned on the insulative liner and over the separation region; a pair of insulator regions each positioned laterally between the semiconductor mandrel and the insulative liner on the sidewall surfaces of each of the pair of transistor sites; and a source/drain epitaxial region positioned over the pair of insulator regions and the semiconductor mandrel, wherein the source/drain epitaxial region laterally abuts the pair of nanosheet stacks.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Min Gyu Sung, Ruilong Xie, Chanro Park, Steven Bentley
  • Publication number: 20180090391
    Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mira Park, Kwan-Yong Lim, Steven Bentley, Amitabh Jain
  • Publication number: 20180053843
    Abstract: Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.
    Type: Application
    Filed: August 19, 2016
    Publication date: February 22, 2018
    Inventors: Brent A. Anderson, Steven Bentley, Kwan-Yong Lim, Hiroaki Niimi, Junli Wang
  • Publication number: 20180033789
    Abstract: We disclose semiconductor devices, comprising a semiconductor substrate comprising a substrate material; and a plurality of fins disposed on the substrate, each fin comprising a lower region comprising the substrate material, a dopant region disposed above the lower region and comprising at least one dopant, and a channel region disposed above the dopant region and comprising a semiconductor material, wherein the channel region comprises less than 1×1018 dopant molecules/cm3, as well as methods, apparatus, and systems for fabricating such semiconductor devices.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Applicants: GLOBALFOUNDRIES INC., International Business Machines Corporation
    Inventors: Steven Bentley, Kwan-Yong Lim, Tenko Yamashita, Gauri Karve, Sanjay Mehta
  • Patent number: 9865682
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 9825032
    Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: November 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Bipul C. Paul
  • Publication number: 20170317169
    Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.
    Type: Application
    Filed: July 18, 2017
    Publication date: November 2, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Deepak Nayak
  • Patent number: 9805988
    Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure including: forming a fin over a substrate within a device region, the fin including alternating layers of a sacrificial material and a semiconductor material, and including a lower channel region; forming a dopant-containing layer over the fin and the substrate; exposing an upper portion of the fin by removing the dopant-containing layer from the upper portion of the fin; removing the sacrificial material from the fin thereby suspending the semiconductor material within the fin between a pair of spacers and over the lower channel region of the fin; performing an anneal to drive in dopants from the dopant-containing layer to the lower channel region of the fin; and forming an active gate over the lower channel region of the fin and substantially surrounding the suspended semiconductor material over the lower channel region of the fin.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Guillaume Bouche
  • Patent number: 9773708
    Abstract: Devices and methods of fabricating vertical field effect transistors on semiconductor devices are provided. One intermediate semiconductor includes: a substrate, a bottom spacer layer above the substrate, a plurality of fins, wherein at least one fin is an n-fin and at least one fin is a p-fin; a high-k layer and a work function metal over the bottom spacer layer and around the plurality of fins; a top spacer above the high-k layer and the work function metal and surrounding a top area of the fins; a top source/drain structure over each fin; a dielectric capping layer over the top source/drain structure; a fill metal surrounding the work function metal; and a liner.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: September 26, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John Zhang, Steven Bentley, Kwan-Yong Lim
  • Publication number: 20170263465
    Abstract: One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin.
    Type: Application
    Filed: May 18, 2017
    Publication date: September 14, 2017
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 9761156
    Abstract: A bow label for a beverage container is disclosed herein. The bow label may include a first sheet at least partially attached to the beverage container. The bow label also may include a second sheet at least partially attached to the first sheet. The first sheet and the second sheet may include a first configuration and a second configuration. In addition, the bow label may include a pull cord disposed between and at least partially attached to the first sheet and the second sheet. In this manner, movement of the pull cord may move the first sheet and the second sheet between the first configuration and the second configuration. In some instances, the second configuration may include a bow-like shape.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: September 12, 2017
    Assignee: THE COCA-COLA COMPANY
    Inventors: Christopher James Bowers, Gregory Steven Bentley
  • Publication number: 20170250250
    Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.
    Type: Application
    Filed: February 29, 2016
    Publication date: August 31, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Deepak Nayak
  • Patent number: 9748335
    Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Deepak Nayak
  • Patent number: 9698025
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 9647086
    Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 9, 2017
    Assignees: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Bentley, Jody Fronheiser, Xin Miao, Joseph Washington, Pierre Morin
  • Patent number: 9613817
    Abstract: A method of enhancing surface diffusion species concentration in source/drain regions includes providing a substrate for an integrated circuit. One of an n-type and a p-type S/D region for a semiconductor device is formed on a surface of the substrate. A top surface of the S/D region is exposed. A diffusion layer is deposited over the top surface of the S/D region, the diffusion layer having a concentration of a diffusion species. The diffusion layer is heated to diffuse the diffusion species into the S/D region to enhance a concentration of the diffusion species proximate the top surface of the S/D region. The diffusion layer is removed from the top surface of the S/D region. A metal layer is deposited over the top surface of the S/D region immediately after removing the diffusion layer. Electrical contacts are formed over the top surface of the S/D region from the metal layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Vimal Kamineni
  • Publication number: 20170053567
    Abstract: A bow label for a beverage container is disclosed herein. The bow label may include a first sheet at least partially attached to the beverage container. The bow label also may include a second sheet at least partially attached to the first sheet. The first sheet and the second sheet may include a first configuration and a second configuration. In addition, the bow label may include a pull cord disposed between and at least partially attached to the first sheet and the second sheet. In this manner, movement of the pull cord may move the first sheet and the second sheet between the first configuration and the second configuration. In some instances, the second configuration may include a bow-like shape.
    Type: Application
    Filed: May 6, 2015
    Publication date: February 23, 2017
    Applicant: THE COCA-COLA COMPANY
    Inventors: Christopher James Bowers, Gregory Steven Bentley
  • Patent number: 9577042
    Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Rohit Galatage