Patents by Inventor Steven Bentley

Steven Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10332969
    Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Patent number: 10312154
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Publication number: 20190148494
    Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, John H. Zhang, Steven Bentley, Hui Zang
  • Patent number: 10283621
    Abstract: Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Hui Zang, Steven Bentley
  • Patent number: 10269812
    Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, John H. Zhang, Steven Bentley, Hui Zang
  • Publication number: 20190115437
    Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 18, 2019
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Patent number: 10256158
    Abstract: Integrated circuit structures include isolation elements extending into a substrate, and source/drain regions of a first transistor contacting the isolation elements. The isolation elements extend from the substrate to the source/drain regions of the first transistor. Isolation layers contact the source/drain regions of the first transistor, and source/drain regions of a second transistor also contact the isolation layers. Thus, the isolation layers are between the source/drain regions of the first transistor and the source/drain regions of the second transistor. Channel regions of the first transistor contact and extend between the source/drain regions of the first transistor, and channel regions of the second transistor contact and extend between the source/drain regions of the second transistor. A gate conductor surrounds sides of the channel region of the first transistor and the channel region of the second transistor.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Puneet H. Suvarna
  • Patent number: 10249710
    Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Deepak Nayak
  • Patent number: 10243073
    Abstract: Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Steven Bentley, Kwan-Yong Lim, Hiroaki Niimi, Junli Wang
  • Publication number: 20190088767
    Abstract: Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 21, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Hui Zang, Steven Bentley
  • Patent number: 10236379
    Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Puneet Harischandra Suvarna, Julien Frougier, Bartlomiej Jan Pawlak
  • Patent number: 10217846
    Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Steven Soss, Hui Zang, Xusheng Wu, Yi Qi, Ajey P. Jacob, Murat K. Akarvardar, Siva P. Adusumilli, Jiehui Shu, Haigou Huang, John H. Zhang
  • Publication number: 20190035938
    Abstract: Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Inventors: Chanro Park, Steven Bentley, Ruilong Xie, Min Gyu Sung
  • Patent number: 10186577
    Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: January 22, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 10170617
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES
    Inventors: Jiseok Kim, Hiroaki Niimi, Hoon Kim, Puneet Harischandra Suvarna, Steven Bentley, Jody A. Fronheiser
  • Publication number: 20180366372
    Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 20, 2018
    Inventors: Puneet H. Suvarna, Steven Bentley, Mark V. Raymond, Peter M. Zeitzoff
  • Patent number: 10157794
    Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Puneet H. Suvarna, Steven Bentley, Mark V. Raymond, Peter M. Zeitzoff
  • Patent number: 10141414
    Abstract: A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 27, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Publication number: 20180337256
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 22, 2018
    Inventors: Brent A. Anderson, Steven Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Publication number: 20180331213
    Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 15, 2018
    Applicant: GLOBAL FOUNDRIES INC.
    Inventors: Steven Bentley, Puneet Harischandra Suvarna, Julien Frougier, Bartlomiej Jan Pawlak