Patents by Inventor Steven Bentley

Steven Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10243073
    Abstract: Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Steven Bentley, Kwan-Yong Lim, Hiroaki Niimi, Junli Wang
  • Publication number: 20190088767
    Abstract: Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 21, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Hui Zang, Steven Bentley
  • Publication number: 20190088764
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: GLBOALFOUNDRIES INC.
    Inventors: Ruilong XIE, Steven BENTLEY, Puneet Harischandra SUVARNA, Chanro PARK, Min Gyu SUNG, Lars LIEBMANN, Su Chen FAN, Brent ANDERSON
  • Patent number: 10236379
    Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Puneet Harischandra Suvarna, Julien Frougier, Bartlomiej Jan Pawlak
  • Patent number: 10217846
    Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Steven Soss, Hui Zang, Xusheng Wu, Yi Qi, Ajey P. Jacob, Murat K. Akarvardar, Siva P. Adusumilli, Jiehui Shu, Haigou Huang, John H. Zhang
  • Publication number: 20190035938
    Abstract: Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Inventors: Chanro Park, Steven Bentley, Ruilong Xie, Min Gyu Sung
  • Patent number: 10186577
    Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: January 22, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 10170617
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES
    Inventors: Jiseok Kim, Hiroaki Niimi, Hoon Kim, Puneet Harischandra Suvarna, Steven Bentley, Jody A. Fronheiser
  • Publication number: 20180366372
    Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 20, 2018
    Inventors: Puneet H. Suvarna, Steven Bentley, Mark V. Raymond, Peter M. Zeitzoff
  • Patent number: 10157794
    Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Puneet H. Suvarna, Steven Bentley, Mark V. Raymond, Peter M. Zeitzoff
  • Patent number: 10141414
    Abstract: A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 27, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Publication number: 20180337256
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 22, 2018
    Inventors: Brent A. Anderson, Steven Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Publication number: 20180331213
    Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 15, 2018
    Applicant: GLOBAL FOUNDRIES INC.
    Inventors: Steven Bentley, Puneet Harischandra Suvarna, Julien Frougier, Bartlomiej Jan Pawlak
  • Patent number: 10056377
    Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Bipul C. Paul
  • Publication number: 20180226505
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.
    Type: Application
    Filed: February 3, 2017
    Publication date: August 9, 2018
    Inventors: Jiseok KIM, Hiroaki NIIMI, Hoon KIM, Puneet Harischandra SUVARNA, Steven BENTLEY, Jody A. FRONHEISER
  • Patent number: 9991352
    Abstract: A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ali Razavieh, Ruilong Xie, Steven Bentley
  • Publication number: 20180145073
    Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.
    Type: Application
    Filed: October 17, 2017
    Publication date: May 24, 2018
    Inventors: Steven BENTLEY, Bipul C. PAUL
  • Publication number: 20180138046
    Abstract: A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 17, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Steven BENTLEY, Ruilong XIE
  • Patent number: 9972494
    Abstract: A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Ruilong Xie
  • Publication number: 20180130895
    Abstract: One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.
    Type: Application
    Filed: November 8, 2016
    Publication date: May 10, 2018
    Inventors: Chanro Park, Steven Bentley, Hoon Kim, Min Gyu Sung, Ruilong Xie