Patents by Inventor Steven Bentley

Steven Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170047425
    Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.
    Type: Application
    Filed: August 14, 2015
    Publication date: February 16, 2017
    Inventors: Steven BENTLEY, Jody FRONHEISER, Xin MIAO, Joseph WASHINGTON, Pierre MORIN
  • Publication number: 20170047404
    Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.
    Type: Application
    Filed: August 13, 2015
    Publication date: February 16, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Steven BENTLEY, Rohit GALATAGE
  • Patent number: 9570588
    Abstract: Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: February 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem Akarvardar, Steven Bentley
  • Patent number: 9530869
    Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Steven Bentley
  • Publication number: 20160268399
    Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.
    Type: Application
    Filed: March 10, 2015
    Publication date: September 15, 2016
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Steven Bentley
  • Patent number: 9439379
    Abstract: A new and distinct Buglossoides arvensis plant named ‘MALIN’ characterized by vigorous plant growth and abundant side shoot development. Plants flower early in May and June and do not require vernalization. Seed germination rate is typically 80%. Seeds of the plant are used in the production of the oil commercially known Ahiflower oil.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: September 13, 2016
    Assignee: NIAB Trading Ltd.
    Inventor: Steven Bentley
  • Publication number: 20160227723
    Abstract: A new and distinct Buglossoides arvensis plant named ‘MALIN’ characterized by vigorous plant growth and abundant side shoot development. Plants flower early in May and June and do not require vernalization. Seed germination rate is typically 80%. Seeds of the plant are used in the production of the oil commercially known Ahiflower oil.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 11, 2016
    Applicant: NIAB
    Inventor: Steven Bentley
  • Patent number: 9406803
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Murat Kerem Akarvardar, Steven Bentley
  • Publication number: 20160190323
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.
    Type: Application
    Filed: April 1, 2015
    Publication date: June 30, 2016
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Murat Kerem Akarvardar, Steven Bentley
  • Publication number: 20160190289
    Abstract: Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure.
    Type: Application
    Filed: October 14, 2015
    Publication date: June 30, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem AKARVARDAR, Steven BENTLEY
  • Publication number: 20160181087
    Abstract: Particle-clean formulations and methods for semiconductor substrates use aqueous solutions of tetraethylammonium hydroxide (“TEAH,” C8H21NO) with or without hydrogen peroxide (H2O2). The solution pH ranges from 8-12.5. At process temperatures between 20-70 C, the TEAH solutions have been observed to remove particles from silicon-germanium (SiGe) with 20-99% Ge content in 15-300 seconds with very little etching (SiGe etch rates<1 nm/min).
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: John Foster, Steven Bentley, Sean Lin, Dave Rath, Muthumanickam Sankarapandian, Ruilong Xie
  • Patent number: 9368578
    Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: June 14, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bartlomiej Jan Pawlak, Steven Bentley, Ajey Jacob
  • Patent number: 9305846
    Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: April 5, 2016
    Assignees: GlobalFoundries Inc., International Business Machines Corporation, Renesas Electronics Corporation
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Steven Bentley, Toshiharu Nagumo, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz
  • Patent number: 9299775
    Abstract: Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Steven Bentley, Kejia Wang, Sylvie Mignot, Shurong Liang
  • Patent number: 9293324
    Abstract: Semiconductor devices including a fin and method of forming the semiconductor devices are provided herein. In an embodiment, a method of forming a semiconductor device includes forming a fin overlying a semiconductor substrate. The fin is formed by epitaxially-growing a semiconductor material over the semiconductor substrate, and the fin has a first portion that is proximal to the semiconductor substrate and a second portion that is spaced from the semiconductor substrate by the first portion. A gate structure is formed over the fin and the semiconductor substrate. The first portion of the fin is etched to form a gap between the second portion and the semiconductor substrate.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Steven Bentley, Ajey P. Jacob
  • Publication number: 20160071929
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Publication number: 20160071845
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Publication number: 20160071930
    Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 9236309
    Abstract: Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Steven Bentley
  • Publication number: 20150340289
    Abstract: Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride.
    Type: Application
    Filed: April 15, 2015
    Publication date: November 26, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Chanro PARK, Steven BENTLEY