Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure including: forming a fin over a substrate within a device region, the fin including alternating layers of a sacrificial material and a semiconductor material, and including a lower channel region; forming a dopant-containing layer over the fin and the substrate; exposing an upper portion of the fin by removing the dopant-containing layer from the upper portion of the fin; removing the sacrificial material from the fin thereby suspending the semiconductor material within the fin between a pair of spacers and over the lower channel region of the fin; performing an anneal to drive in dopants from the dopant-containing layer to the lower channel region of the fin; and forming an active gate over the lower channel region of the fin and substantially surrounding the suspended semiconductor material over the lower channel region of the fin.

Abstract: Devices and methods of fabricating vertical field effect transistors on semiconductor devices are provided. One intermediate semiconductor includes: a substrate, a bottom spacer layer above the substrate, a plurality of fins, wherein at least one fin is an n-fin and at least one fin is a p-fin; a high-k layer and a work function metal over the bottom spacer layer and around the plurality of fins; a top spacer above the high-k layer and the work function metal and surrounding a top area of the fins; a top source/drain structure over each fin; a dielectric capping layer over the top source/drain structure; a fill metal surrounding the work function metal; and a liner.

Abstract: One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin.

Abstract: A bow label for a beverage container is disclosed herein. The bow label may include a first sheet at least partially attached to the beverage container. The bow label also may include a second sheet at least partially attached to the first sheet. The first sheet and the second sheet may include a first configuration and a second configuration. In addition, the bow label may include a pull cord disposed between and at least partially attached to the first sheet and the second sheet. In this manner, movement of the pull cord may move the first sheet and the second sheet between the first configuration and the second configuration. In some instances, the second configuration may include a bow-like shape.

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

Abstract: A method of enhancing surface diffusion species concentration in source/drain regions includes providing a substrate for an integrated circuit. One of an n-type and a p-type S/D region for a semiconductor device is formed on a surface of the substrate. A top surface of the S/D region is exposed. A diffusion layer is deposited over the top surface of the S/D region, the diffusion layer having a concentration of a diffusion species. The diffusion layer is heated to diffuse the diffusion species into the S/D region to enhance a concentration of the diffusion species proximate the top surface of the S/D region. The diffusion layer is removed from the top surface of the S/D region. A metal layer is deposited over the top surface of the S/D region immediately after removing the diffusion layer. Electrical contacts are formed over the top surface of the S/D region from the metal layer.

Abstract: A bow label for a beverage container is disclosed herein. The bow label may include a first sheet at least partially attached to the beverage container. The bow label also may include a second sheet at least partially attached to the first sheet. The first sheet and the second sheet may include a first configuration and a second configuration. In addition, the bow label may include a pull cord disposed between and at least partially attached to the first sheet and the second sheet. In this manner, movement of the pull cord may move the first sheet and the second sheet between the first configuration and the second configuration. In some instances, the second configuration may include a bow-like shape.

Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.

Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

Abstract: Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure.

Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.

Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.

Abstract: A new and distinct Buglossoides arvensis plant named ‘MALIN’ characterized by vigorous plant growth and abundant side shoot development. Plants flower early in May and June and do not require vernalization. Seed germination rate is typically 80%. Seeds of the plant are used in the production of the oil commercially known Ahiflower oil.

Abstract: A new and distinct Buglossoides arvensis plant named ‘MALIN’ characterized by vigorous plant growth and abundant side shoot development. Plants flower early in May and June and do not require vernalization. Seed germination rate is typically 80%. Seeds of the plant are used in the production of the oil commercially known Ahiflower oil.