Abstract: An information handling system includes a processing unit that is coupled to a memory device by a communication channel. The processing unit includes a memory controller and is configured to host a basic input output system (BIOS). The memory device, which may include a dual in-line memory module (DIMM), stores serial presence detect (SPD) information. In an embodiment, the BIOS obtains the SPD information and parameters of the communication channel, such as channel impedance and channel length. In this embodiment, the BIOS uses a look-up table to determine an equalization of the communication channel based on the obtained SPD information and the obtained parameters of the communication channel, and utilizes the memory controller to set the equalization of the communication channel, such as by setting or controlling settings of transmission and reception components of the memory controller.

Abstract: An information handling system may include a central processing unit (CPU) and a device. The CPU may have an I/O system and be configured to host a BIOS. The device may be communicatively connected to the I/O system of the CPU by a connection. The BIOS may determine a communication protocol used by the device for communication and set an equalization of the I/O system for communication with the device based on the communication protocol used by the device.

Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communica

Abstract: A receiver includes signal lanes to receive associated data bit streams, and a control module. The signal lanes each include configurable equalization modules to provide a selectable compensation value to the associated data bit stream. The control module performs back channel adaptations on each data bit stream to achieve a target bit error rate for the associated signal lane, determines a most common set of compensation values from the performance of the back channel adaptations, determines whether the compensation value is within a predetermined boundary for that selectable compensation value, and provides an alert when a first compensation value of the most common set of compensation values is not within the predetermined boundary for the first compensation value.

Abstract: An information handling system with improved memory transactions includes a data mover configured to generate a transaction layer packet (TLP) hint when a descriptor includes a write operation to a persistent memory. A logic block may perform a persistent write based on the TLP hint.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communica

Abstract: An information handling system includes processors disposed in sockets, and interconnect links providing point-to-point links between the sockets. One of the processors determines an arrangement of the processors, memories and the interconnect links, and determines a value for each of the processors, each of the memories, and each of the interconnect links. The processor calculates interconnect link bandwidth values for each of the interconnect links based at least in part on the determined value and the arrangement of the processors, the memories and the interconnect links. The processor also populates an interconnect bandwidth table using the interconnect link bandwidth values.

Abstract: An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed.

Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

Abstract: An information handling system includes a power assist unit (PAU) and a baseboard management controller (BMC). The PAU is coupled to a power rail and includes a power storage element, a converter coupled to the power storage element and the power rail, and a controller. The controller receives a current level indication indicating a current provided to a load of the information handling system, directs the converter to provide power from the power storage element to the power rail when the current level indication is greater than a threshold level, directs the converter charge the power storage element from the power rail when the current level indication is greater than the threshold level, and provides a charge level indication that indicates an amount of charge on the power storage unit. The BMC receives the charge level indication, and sets a peak power limit for the information handling system based on the charge level indication.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

Abstract: An information handling system includes a plurality of storage class memory (SCM) devices and a processor. Each SCM device is configured to determine a health indication of the SCM device. The processor is configured to execute code to provide a basic input/output system (BIOS). The BIOS receives the health indications, ranks the SCMs based upon the health indications, determines that a first BIOS function has a first quality of service level, and allocates the first BIOS function to a first SCM based upon the first quality of service level, wherein the first SCM has a highest rank of the SCMs.

Abstract: An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed.

Abstract: An information handling system includes a memory controller and a Dual In-Line Memory Module (DIMM) including a Dynamic Random Access Memory (DRAM) device. The DRAM device is configured to detect an Error Correcting Code (ECC) bit error for a data transaction within the DRAM device, determine if the ECC bit error results in an ECC error threshold being exceeded, and provide an alert signal to the memory controller in response to determining that the ECC bit error resulted in the ECC error threshold being exceeded.

Abstract: An information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a memory controller. The memory controller may be configured to monitor memory input/output traffic to each of the plurality of non-volatile memories, determine a quality of service associated with each of the plurality of non-volatile memories based on such monitoring, and based on such monitoring and the qualities of service associated with the plurality of non-volatile memories, reroute input/output data associated with a first non-volatile memory of the plurality of non-volatile memories to a second non-volatile memory of the plurality of non-volatile memories.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine that a first memory unit (MU) and a second MU of a first channel of a memory module are associated with an issue; may configure a control device to utilize a third MU in place of the first MU; and may configure the control device to utilize a fourth MU, of a second channel of the memory module, in place of the second MU. In one or more embodiments, multiple MUs of the first channel, other than the first and second MUs, may store a first portion of data; the fourth MU may store a second portion of the data; the multiple MUs, other than the first and second MUs, may provide the first portion of the data to a processor; and the fourth MU may provide the second portion of the data to the processor.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine that a first memory unit (MU) and a second MU of a first channel of a memory module are associated with an issue; may configure a control device to utilize a third MU in place of the first MU; and may configure the control device to utilize a fourth MU, of a second channel of the memory module, in place of the second MU. In one or more embodiments, multiple MUs of the first channel, other than the first and second MUs, may store a first portion of data; the fourth MU may store a second portion of the data; the multiple MUs, other than the first and second MUs, may provide the first portion of the data to a processor; and the fourth MU may provide the second portion of the data to the processor.

Abstract: A dual-channel Dual In-Line Memory Module (DIMM) is configured to provide memory transactions on a first memory channel and a second memory channel. The dual-channel DIMM includes a first bank of Dynamic Random Access Memory (DRAM) devices configured to provide a first memory transaction on the first memory channel, a second bank of DRAM devices configured to provide a second memory transaction on the second memory channel, and a plurality of back door communication paths, each back door communication path being between a data bit of the first bank of DRAM devices and a corresponding data bit of the second bank of DRAM devices.