Abstract: In accordance with embodiments of the present disclosure, a method may include, during boot of an information handling system, determining a first amount of energy required by the information handling system to flush a cache integral to the information handling system to memory integral to the information handling system in response to a power loss of one or more power supplies for supplying electrical energy to the information handling system, determining whether a second amount of energy available for hold-up of one or more power supplies in response to the power loss exceeds the first amount of energy, and responsive to determining whether the second amount of energy exceeds the first amount of energy, configuring the cache.

Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

Abstract: A receiver of a serial communication channel including a memory to store an initial channel characteristic of the serial communication channel, a detector to measure a current channel characteristic of the serial communication channel, and a processor to compare the initial channel characteristic to the current channel characteristic, and to provide an indication when the difference between the initial channel characteristic to the current channel characteristic is greater than a threshold.

Abstract: A dual axial cable includes first and second signal conductors, a shield, and a drain wire. The first and second signal conductors transmit a differential signal. The shield is spirally wrapped around the first and second conductors, and causes a resonant characteristic of the dual axial cable. The drain wire provides a return path for the differential signal in the dual axial cable. The drain wire is roughened to a specific amount of roughness, which reduces signal loss at resonant frequencies of the resonant characteristic caused by the shield.

Abstract: An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration.

Abstract: A serial data channel includes a transmitter with a jitter generator that receives a jitter setting and injects a timing delay into an output signal of the transmitter in response to the jitter setting. The serial data channel further includes a receiver with an eye detector configured to evaluate a signal eye of the received output signal. The serial data channel provides a plurality of jitter settings to the jitter generator, and evaluates a plurality of signal eyes of the received output signal, where each signal eye of the plurality of signal eyes being associated with a particular received output signal generated in response to a particular one of the plurality of jitter settings. The serial data channel further selects a particular jitter setting of the plurality of jitter settings based upon the evaluation of the associated received output signal.

Abstract: A high-speed serial interface includes a transmitter having an output module with settings that select an output impedances of the output module and a tuning value for the output impedance, and a receiver having a plurality of compensation modules each to provide a selectable level of equalization to a data bitstream from the transmitter, and a control module that directs the transmitter to successively select each of the tuning values, that directs the compensation modules, for each tuning value, to successively select each of the levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, and that selects a particular tuning value based upon the indications of the performance level of the receiver.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a power system comprising a plurality of voltage regulator phases, wherein at least one of the plurality of voltage regulator phases comprises an allocable voltage regulator phase that is configured to be selectively allocated to one of at least a first voltage rail and a second voltage rail of the information handling system based on a hardware configuration of the information handling system.

Abstract: A thermal response engine on an information handling system compares a processor thermal response to a predetermined workload with an expected thermal response to the predetermined workload in order to validate that a heat sink disposed on the processor matches a heat sink used by a thermal controller profile to manage thermal conditions of the information handling system. If the heat sink thermal characteristics fail to match up with expected thermal characteristics, the thermal response engine provides the thermal controller with an appropriate thermal profile and alerts the end user of an incompatibility.

Abstract: A basic input/output system may be configured to, during boot of an information handling system in a pre-operating system environment of the information handling system, calculate an amount of energy required to perform a persistent memory save operation in a persistent memory of the information handling system in order to transfer data from a volatile memory of the persistent memory communicatively coupled to the processor to a non-volatile memory of the persistent memory communicatively coupled to the volatile memory, cause charging of an energy storage device for providing electrical energy to perform persistent memory save operations at least until a charging level of the energy storage device satisfies the amount of energy, and boot to an operating system of the information handling system responsive to the charging level of the energy storage device satisfying the amount of energy.

Abstract: An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory device(s). A memory controller writes data to the volatile memory device(s) and, in response, updates a cache tracking database. The memory controller then writes a subset of the data to the SCM subsystem subsequent to the writing of that data to the volatile memory device(s) and, in response, updates the cache tracking database. The memory controller then receives a shutdown signal and, in response, copies the cache tracking database to the volatile memory device(s) in the NVDIMM-N subsystem. The NVDIMM-N subsystem then copies at least some of the data and the cache tracking database from the volatile memory device(s) to the non-volatile memory device(s) prior to shutdown. The data and the cache tracking database may then be retrieved from non-volatile memory device(s) when the system is restored.

Abstract: An information handling system may implement a method for controlling cache flush size by limiting the amount of modified cached data in a data cache at any given time. The method may include keeping a count of the number of modified cache lines (or modified cache lines targeted to persistent memory) in the cache, determining that a threshold value for modified cache lines is exceeded and, in response, flushing some or all modified cache lines to persistent memory. The threshold value may represent a maximum number or percentage of modified cache lines. The cache controller may include a field for each cache line indicating whether it targets persistent memory. Limiting the amount of modified cached data at any given time may reduce the number of cache lines to be flushed in response to a power loss event to a number that can be flushed using the available hold-up energy.

Abstract: A voltage regulator circuit comprises a plurality of voltage regulator phases, a first load output coupled to the plurality of voltage regulator phases for providing a first output voltage, a first coupling inductor having a first winding and a second winding, the first winding coupled in series between a first voltage regulator phase of the plurality of voltage regulator phases and the first load output, a second load output coupled to the second winding for providing a second output voltage, and a first switch coupled in series with the second winding. A method comprises detecting a startup event; determining an installed processor type; retrieving a configuration parameter value; providing a first output voltage at a first load output; providing, at a second load output coupled to the second winding, a second output voltage; and controlling a first duty cycle of a first switch coupled in series with the second winding.

Abstract: A dual inline memory module includes a local memory and a non-volatile memory. The local memory stores data during normal operation of the dual inline memory module. The non-volatile memory includes a first portion and a second portion. The first portion stores the data located in the local memory in response to a power failure of an information handling system in communication with the dual inline memory module. The second portion stores configuration information for the dual inline memory module. The configuration information is utilized to set up the dual inline memory module in a new information handling system.

Abstract: An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory device(s). A memory controller writes data to the volatile memory device(s) and, in response, updates a cache tracking database. The memory controller then writes a subset of the data to the SCM subsystem subsequent to the writing of that data to the volatile memory device(s) and, in response, updates the cache tracking database. The memory controller then receives a shutdown signal and, in response, copies the cache tracking database to the volatile memory device(s) in the NVDIMM-N subsystem. The NVDIMM-N subsystem then copies at least some of the data and the cache tracking database from the volatile memory device(s) to the non-volatile memory device(s) prior to shutdown. The data and the cache tracking database may then be retrieved from non-volatile memory device(s) when the system is restored.

Abstract: A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured to perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values.

Abstract: A serial communication link includes a receiver and a transmitter coupled to the receiver by a first serial communication lane operating at a first speed, and a second serial communication lane operating at a second speed. The second speed is slower than the first speed. The transmitter can include bit steering logic that receives a data stream, provides a first number of bits of the data stream to the first serial communication lane, and provides a second number of bits to the second serial communication lane. The proportion of the first number of bits to the second number of bits is the same as a proportion of the first speed to the second speed.

Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.

Abstract: A memory protection module includes comparison logic that has a write-once window CSR that stores a memory address range, and window protection logic. The comparison logic receives a memory write transaction, determines a memory address of the memory write transaction, and provides an indication as to whether or not the memory address is included in the memory address range. The window protection logic receives the memory transaction receives the indication from the comparison logic, allows the memory write transaction to proceed in response to the indication indicating that the memory address is not included in the memory address range, and drops the memory write transaction in response to the indication indicating that the memory address is included in the memory address range.

Abstract: An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory device(s). A memory controller writes data to the volatile memory device(s) and, in response, updates a cache tracking database. The memory controller then writes a subset of the data to the SCM subsystem subsequent to the writing of that data to the volatile memory device(s) and, in response, updates the cache tracking database. The memory controller then receives a shutdown signal and, in response, copies the cache tracking database to the volatile memory device(s) in the NVDIMM-N subsystem. The NVDIMM-N subsystem then copies at least some of the data and the cache tracking database from the volatile memory device(s) to the non-volatile memory device(s) prior to shutdown. The data and the cache tracking database may then be retrieved from non-volatile memory device(s) when the system is restored.