Abstract: Systems and methods for grooved vias are described. For example, a method may include: drilling a via hole in a Printed Circuit Board (PCB), where the PCB comprises a first layer having a first trace and a second layer having a second trace, the via hole includes a first portion between the first layer and the second layer and a second portion between the second layer and a bottom surface of the PCB, and the via hole is configured to couple the first trace to the second trace through the first portion; after drilling the via hole, creating a rough internal surface in at least the second portion of the via hole that is configured to reduce a resonance of a signal transmitted from the first trace to the second trace; and forming a via by filling the first and second portions of the via hole with conductive material.

Abstract: A server includes slots for adding peripheral devices, and a server chassis having a openings corresponding to the slots. A display mounted on the server chassis proximate the opening displays slot characteristics, slot status information, or user defined information corresponding to the slots.

Abstract: An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration.

Abstract: A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A method validates whether a component/device installed within an information handling system (IHS) is an OEM (original equipment manufacturer) programmed device, by: reading identification (ID) data and an identifier code from the target device; generating a unique encrypted sequence using the ID data; providing a unique validation check code based on the ID data; generating a component validation code corresponding to the target device via a decryption process involving the unique encrypted sequence; and comparing the component validation code to the validation check code. The method further includes: in response to the component validation code matching the validation check code, identifying the target device as an OEM programmed device with a valid identifier code stored as the identifier code; and enabling certain processes reserved for only verified OEM programmed devices. The decryption process reverses an encryption process utilized when generating the unique OEM identifier code of the target device.

Abstract: An information handling system may include a central processing unit (CPU) and a device. The CPU may have an I/O system and be configured to host a BIOS. The device may be communicatively connected to the I/O system of the CPU by a connection. The BIOS may determine a communication protocol used by the device for communication and set an equalization of the I/O system for communication with the device based on the communication protocol used by the device.

Abstract: In accordance with embodiments of the present disclosure, a voltage rectifier may include an alternating-current-to-direct-current (AC/DC) converter configured to convert an alternating current (AC) source voltage to a first direct current (DC) voltage and a direct-current-to-direct-current (DC/DC) converter configured to convert the first DC voltage to a second DC voltage for delivery to a load of the voltage rectifier, wherein the DC/DC converter is configured to operate in a plurality of operating modes in response to a failure of the AC source voltage. The plurality of operating modes may include a first hold-up mode in which a gain of the DC/DC converter is a first gain and a second hold-up mode in which the gain of the DC/DC converter is a second gain.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A server includes slots for adding peripheral devices, and a server chassis having a openings corresponding to the slots. A display mounted on the server chassis proximate the opening displays slot characteristics, slot status information, or user defined information corresponding to the slots.

Abstract: An information handling system may include a processing unit and a memory device. The processing unit includes a memory controller and is configured to host a BIOS. The memory device is communicatively connected to the memory controller by a communication channel and stores memory device information. The BIOS obtains the memory device information and sets an equalization of the communication channel based on the memory device information. The BIOS may further set the equalization of the communication channel based on parameters of the communication channel.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a primary persistent memory comprising a volatile memory for storing data and a non-volatile memory for receiving data transferred from the volatile memory in response to a power loss of the information handling system. The information handling system may also include an alternate persistent memory instructions embodied in non-transitory computer readable media, the instructions for causing a processor communicatively coupled to the primary persistent memory and the alternate persistent memory to, responsive to a vulnerability of a persistence of the primary persistent memory, transfer application data from the primary persistent memory to the alternate persistent memory.

Abstract: A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device.

Abstract: An information handling system includes a memory controller and a Dual In-Line Memory Module (DIMM) including a Dynamic Random Access Memory (DRAM) device. The DRAM device is configured to detect an Error Correcting Code (ECC) bit error for a data transaction within the DRAM device, determine if the ECC bit error results in an ECC error threshold being exceeded, and provide an alert signal to the memory controller in response to determining that the ECC bit error resulted in the ECC error threshold being exceeded.

Abstract: A dual-channel Dual In-Line Memory Module (DIMM) is configured to provide memory transactions on a first memory channel and a second memory channel. The dual-channel DIMM includes a first bank of Dynamic Random Access Memory (DRAM) devices configured to provide a first memory transaction on the first memory channel, a second bank of DRAM devices configured to provide a second memory transaction on the second memory channel, and a plurality of back door communication paths, each back door communication path being between a data bit of the first bank of DRAM devices and a corresponding data bit of the second bank of DRAM devices.

Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

Abstract: A voltage regulator circuit comprises a plurality of voltage regulator phases, a first load output coupled to the plurality of voltage regulator phases for providing a first output voltage, a first coupling inductor having a first winding and a second winding, the first winding coupled in series between a first voltage regulator phase of the plurality of voltage regulator phases and the first load output, a second load output coupled to the second winding for providing a second output voltage, and a first switch coupled in series with the second winding. A method comprises detecting a startup event; determining an installed processor type; retrieving a configuration parameter value; providing a first output voltage at a first load output; providing, at a second load output coupled to the second winding, a second output voltage; and controlling a first duty cycle of a first switch coupled in series with the second winding.

Abstract: A process may involve assembling a device at a device assembler. The process may include receiving a set of components, where each component of the set of components may be associated with a respective memory storing a set of characteristics of the component. The process may include assembling the set of components into the device at the device assembler. The process may also include accessing each respective memory of the components to read the sets of characteristics stored in the respective memories, and determining from the sets of characteristics of the components the characteristics of the device.

Abstract: An information handling system may include a first computing device, a second computing device, a connector device connecting the first computing device and the second computing device, and a controller. The connector device may be assembled from a set of components, where one or more of the components have a memory storing signal integrity characteristics for the component. The controller may be connected to the component memories, and may also be connected to the first computing device and the second computing device.

Abstract: A system includes a memory device and a memory controller. The memory device has a data pin and a first available pin. The memory controller has a data pin coupled to the data pin of the memory device, and has a first available pin coupled to the first available pin of the memory device. The memory controller transfers memory data on the first available pin of the memory controller, and the memory device receives memory data on the first available pin of the memory device.