Abstract: A structure of memory device with thin film transistor is proposed. The structure of the memory device includes a substrate. The substrate has shallow trench isolation structures, a thin film transistor, a memory cell transistor, a memory peripheral transistor, and logic circuit transistor. The shallow trench isolation structures are located in the memory cell region, the logic circuit region, and also on the memory peripheral region to isolate the memory peripheral region from the memory cell region and the logic circuit region. The thin film transistor with a thin film substrate is located above the shallow trench isolation structure at the logic circuit region. A method for fabricating the memory device with thin film transistor is also proposed, where a thin film conductive layer is formed over the substrate at the logic circuit region to serve as the thin film transistor substrate.

Abstract: The present invention provides a method for manufacturing a MOS transistor of an embedded memory on the surface of semiconductor wafer. The method of present invention is first to define a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to depose a dielectric layer, a undoped polysilicon layer, a silicide layer, a doped polysilicon layer, a protection layer and a photoresist layer sequentially. Next, a plurality of gate patterns on the memory array area is defined and the protection layer is etched to the surface of the doped polysilicon layer. Then a plurality of gate patterns on the periphery circuit region is defined in and the doped polysilicon layer, the silicide layer and the undoped polysilicon layer are etched to the surface of the dielectric layer so as to form gates of each MOS transistors in the memory array area and periphery circuit region. Finally a spacer and source and drain region are formed around each gate.

Abstract: The present invention provides a method for manufacturing a MOS transistor of an embedded memory on the surface of a semiconductor wafer. The method of the present invention involves the deposition of a first dielectric layer and an undoped polysilicon layer, respectively, in the periphery circuit region of the silicon substrate of the semiconductor wafer. Thereafter, a plurality of gates and lightly doped drains of the MOS transistors are formed in the memory array area of the semiconductor wafer, with each gate comprising a second dielectric layer, a doped polysilicon layer, a silicide layer and a protection layer, respectively. Next, both the undoped polysilicon layer and the first dielectric layer in the periphery circuit region are etched to form gates of each MOS transistor in the periphery circuit region. Finally, lightly doped drains, spacers, sources and drains of each MOS transistor in the periphery circuit region are formed.

Abstract: A memory array area and a periphery circuit region on the surface of a semiconductor wafer are defined, and a gate oxide layer, an polysilicon layer and a dielectric layer are sequentially formed on the wafer. Next, the polysilicon layer in the memory array area is implanted to form a doped polysilicon layer. The doped polysilicon layer in the memory array area is etched down to a predetermined depth and the dielectric layer in the memory array area is removed. A silicide layer and a protection layer are formed on the surface of the semiconductor wafer. An etching process is used to form a plurality of gates in the memory array area and an in-situ etching of the protection layer and the silicide layer in the periphery circuit region is performed. Finally, the polysilicon layer in the periphery circuit region is etched to form a plurality of gates. A spacer, a source and a drain are formed around each gate.

Abstract: A post-etching cleaning method for removing high molecular weight compounds formed after an etching operation. After a dual damascene opening is formed by etching a dielectric layer over a substrate, a two-stage wet cleaning operation is conducted. In the first wet cleaning, a cleaning solution is used to wash the substrate. The cleaning solution contains hydrogen peroxide and benzotriazole. In the second wet cleaning, inorganic acid solution is used.

Abstract: A method of cleaning a dual damascene structure includes forming a first conductive layer in a substrate. A dielectric layer is formed over the substrate. A dual damascene opening is formed in the dielectric layer to expose the first conductive layer. A H2O2 based aqueous solution is used to remove polymer residues in the dual damascene opening. A temperature of the H2O2 based aqueous solution is controlled so that the first conductive layer is not corroded. A diluted HF solution or a diluted HF and HCl solution is used to remove the polymer residues. A second conductive layer is formed over the substrate to fill the dual damascene opening. A chemical mechanical polishing process is performed with the dielectric layer serving as a polishing stop to remove the second conductive layer outside the dual damascene opening. A H2O2 based aqueous solution is used to clean the hydrocarbon particulates from the chemical mechanically polishing step.

Abstract: A memory array area and a periphery circuit region on the surface of a semiconductor wafer are defined, and a gate oxide layer and an undoped polysilicon layer are sequentially formed on the wafer. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer, followed by etching of the doped polysilicon layer in the memory array area down to a predetermined thickness. Next, a silicide layer and a protection layer are formed on the surface of the semiconductor wafer. A photo-etching-process (PEP) is used to etch portions of the protection layer, the silicide layer, the undoped polysilicon layer and the doped polysilicon layer to form a plurality of gates. Finally, a LDD and spacers of each MOS transistor, and a source and a drain of each MOS transistor in the periphery circuit region are formed.

Abstract: A method of fabricating a memory device and a logic device on the same chip is described, wherein the memory device has a first gate on a first region of the chip, and wherein the logic device has a second gate with a sidewall on a second region of the chip. A conductive layer and a first suicide layer are sequentially formed over the first and the second regions of the chip. Over the first region of the chip, the first silicide layer and the conductive layer are patterned to form the first gate. Ions are first implanted into the first region of the chip, by using the first gate as a mask, to form a first doped region. A dielectric layer is formed to cap the first gate, the first doped region and the first region of the chip. The first silicide layer over the second region of the chip is removed. Over the second region of the chip, the conductive layer is patterned to form the second gate.

Abstract: The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of thecapacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

Abstract: The present invention provides a method for the formation of contact plugs of an embedded memory. The method first forms a plurality of MOS transistors on a defined memory array region and periphery circuit region of the semiconductor wafer. Then, a first dielectric layer is formed on the memory array region, and plurality of landing pads is formed in the first dielectric layer. Next, both a stop layer and a second dielectric layer are formed, respectively, on the surface of semiconductor wafer. A PEP process is then used to form a plurality of contact plug holes in the second dielectric layer in both the memory array region and the periphery circuit region. Finally, a conductive layer is filled into each hole to form in-situ each contact plug in both the memory array region and the periphery circuit region.

Abstract: The present invention provides a method for forming an embedded memory MOS. The method involves first forming a first dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer, followed by the formation of a protective layer on the surface of the semiconductor wafer. Thereafter, a first photolithographic and etching process (PEP) is used to etch the protective layer and the doped polysilicon layer in the memory array area to forma plurality of gates, and to form lightly doped drains (LDD) adjacent to each gate. A silicon nitride layer and a second dielectric layer are formed, followed by their removal in the periphery circuits region.

Abstract: A memory array area and a periphery circuit region on the surface of a semiconductor wafer are defined, and a gate oxide layer and an undoped polysilicon layer are sequentially formed on the wafer. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer, followed by etching of the doped polysilicon layer in the memory array area down to a predetermined thickness. Next, a silicide layer and a protection layer are formed on the surface of the semiconductor wafer. A photo-etching-process (PEP) is used to etch portions of the protection layer, the silicide layer, the undoped polysilicon layer and the doped polysilicon layer to form a plurality of gates. Finally, a LDD and spacers of each MOS transistor, and a source and a drain of each MOS transistor in the periphery circuit region are formed.

Abstract: The present invention provides a method to make a local interconnect in an embedded memory. The method first involves defining both a memory array area and a periphery circuit area on the surface of a semiconductor wafer. Then, a plurality of gates and lightly doped drains (LDD) are separately formed in the memory array area and in the periphery circuit area. A silicon nitride layer and a dielectric layer are then formed, respectively, on the surface of the semiconductor wafer and on each gate. Next, a plurality of landing via holes and local interconnect holes are separately formed in the dielectric layer in the memory array area and in the periphery circuit area, followed by the filling of an electrical conducting layer in each hole to simultaneously form a landing via and local interconnect. Then, the dielectric layer and a portion of the silicon nitride layer in the periphery circuit area are removed to form a spacer on either side of each gate in the periphery circuit area.

Abstract: The present invention provides a method of manufacturing a MOS transistor of an embedded memory. The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to deposit a gate oxide layer, an undoped polysilicon layer and a dielectric layer, respectively. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer followed by the removal of the dielectric layer in the memory array area. Thereafter, a metallic silicide layer and a passivation layer are formed, respectively, on the surface of the semiconductor wafer. The passivation layer, the metallic silicide layer and the doped polysilicon layer are then etched to form a plurality of gates in the memory array area. Next, the passivation layer, the metallic silicide layer and the dielectric layer in the periphery circuit region are removed.

Abstract: The present invention provides a method for forming an embedded memory MOS. The method involves first forming a dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer. Thereafter, a protective layer is formed on the surface of the semiconductor wafer, followed by a first photolithographic and etching process(PEP) to define a plurality of gate patterns in the protective layer in the memory array area. Then, a second PEP is applied to etch the undoped polysilicon layer in the periphery circuits region and the doped polysilicon layer in the memory array area to simultaneously form a gate of each MOS in the periphery circuits region and the memory array area.

Abstract: The present invention provides a method to form a dual damascene opening by a liquid phase deposition method. The method can avoid the photoresist left in the via hole and the etching profile of the trench distorted, such will affect the formation of dual damascene opening. The liquid phase deposition is a selectively depositing method, so silicon dioxide will be deposited on the dielectric layer but not on the photoresist. The liquid phase deposition is performed at a temperature range from about 25° C. to about 40° C., which is different from those prior deposition methods which are carried out at a temperature about several hundred degrees centigrade. The liquid used in the liquid phase deposition method was prepared by dissolving highly purified silica particles in hydrofluosilicic acid at 35° C.

Abstract: The invention describes an embedded dynamic random access memory (DRAM) fabrication method. After several landing pads in the memory cell region of a substrate have been formed, a bit-line contact opening and first contact opening are formed simultaneously. The bit-line contact opening exposes the landing pad and the first contact opening exposes the NMOS of the periphery circuit region. An N-type ion implantation is performed to implant N-type ions into the landing pad the NMOS. After a bit-line contact, a first contact, and a bit-line have been formed, a storage node contact opening and a second contact opening are formed simultaneously. The storage node contact opening exposes another landing pad and the second contact opening exposes a P-type MOS in the periphery circuit region. A P-type ion implantation step is conducted to implant P-type ions into the landing pad and the PMOS exposed by the second contact opening.

Abstract: The invention describes an embedded dynamic random access memory (DRAM) fabrication method. After several landing pads in the memory cell region of a substrate have been formed, a bit-line contact opening and first contact opening are formed simultaneously. The bit-line contact opening exposes the landing pad and the first contact opening exposes the NMOS of the periphery circuit region. An N-type ion implantation is performed to implant N-type ions into the landing pad the NMOS. After a bit-line contact, a first contact, and a bit-line have been formed, a storage node contact opening and a second contact opening are formed simultaneously. The storage node contact opening exposes another landing pad and the second contact opening exposes a P-type MOS in the periphery circuit region. A P-type ion implantation step is conducted to implant P-type ions into the landing pad and the PMOS exposed by the second contact opening.

Abstract: A method of forming a dynamic random access memory. A substrate having a memory cell region and a logic circuit region is provided. The substrate also has a first dielectric layer thereon. The first dielectric layer in the memory cell region has a bit line and a node contact while the first dielectric layer in the logic circuit region has a first metallic interconnect. An intermediate dielectric layer is formed over the first dielectric layer such that the intermediate dielectric layer in the logic circuit region has a second metallic interconnect that connects electrically with the first metallic interconnect. A capacitor is formed in the intermediate dielectric layer within the memory cell region. A second dielectric layer is formed over the substrate. A third metallic interconnect is formed in the second dielectric layer such that the third metallic interconnect and the second metallic interconnect are electrically connected.

Abstract: The present invention provides a method to integrate the process of manufacturing an embedded memory and the sequential process of forming a landing via and a strip contact in the embedded memory. The method involves first defining a memory array region and a periphery circuit region on the surface of a silicon substrate of a semiconductor wafer. Next, a plurality of gates and lightly doped drains are separately formed in the memory array region and the periphery circuit region. A silicon nitride layer then covers the surface of each gate in the memory array region, and forms a spacer on either side of each gate in the periphery circuit region. Then, a dielectric layer is formed on the surface of the semiconductor wafer, and a landing via hole and a strip contact hole are separately formed in the dielectric layer in the memory array region and the periphery circuit region, respectively. Finally, each hole is filled with a conductive layer to form in-situ each landing via and strip contact.