Abstract: A method of fabricating a dynamic random memory. On a semiconductor substrate comprising a memory cell region and a periphery circuit region, a first field implantation and a first anti-punch through implantation are performed. Using a photo-resist layer formed to cover the memory cell region as a mask, the periphery circuit region is performed with a second field implantation and a second anti-punch through implantation.

Abstract: An SRAM is formed having the six transistor cell. The pull down transistors are formed so that no arsenic is implanted into the drains of the pull down transistors so that the drains of the pull down transistors are doped only by phosphorus implantation. The sources of the pull down transistors are doped with an LDD configuration of phosphorus ions and then a further implantation of arsenic ions is performed. This can conveniently be accomplished by providing an opening in the mask used to implant impurities into the source/drain regions of the ESD protection circuit.

Abstract: A method of fabricating cylinder capacitors is provided comprising forming a first conductive layer and a dielectric layer on the semiconductor substrate. A via is formed in the dielectric layer. Then, a second conductive layer and a top oxide layer are formed on the dielectric layer. Part of the top oxide layer and the second conductive layer is removed by pattering the photoresist layer. A first spacer is formed at a side wall of the top oxide layer and the second conductive layer. The second conductive layer is etched by using the top oxide layer and the first spacer as a mask. Then, the top oxide layer is removed to form a second spacer. The second spacer is used as a mask in etching the second conductive layer to form a cup-shaped lower electrode. Further, a dielectric film layer and an upper electrode are formed to make a cylinder capacitor.

Abstract: A triple-well structure for semiconductor IC devices such as an SRAM IC device and a process for its fabrication, that allows for improved data storage stability as well as improved immunity capability against interference from device I/O bouncing and alpha particles. The triple-well structure includes at least one P-well in a P-type substrate, a number of N-wells, and a retrograde P-well formed within one of the N-wells. The process for fabricating the triple-well structure includes first implanting boron ions in the P-type substrate. A photomask is subsequently formed for the implantation of phosphorous ions in the region where a P-type MOS transistor is to be fabricated. A high temperature drive-in procedure is then employed to form a P-well and a number of N-wells. A selected area of one of the N-wells where an N-type MOS transistor is defined is then subjected to boron ion implantation, which is followed by an annealing procedure to form the retrograde P-well.

Abstract: A method for fabricating DRAM capacitor which includes forming a transistor having a source/drain regions and a gate electrode above a silicon substrate; then, forming sequentially a stack of layers including a first insulating layer, a second insulating layer, a third insulating layer and a hard mask layer over the transistor; subsequently, patterning and etching the hard mask layer. Thereafter, an oxide layer is formed over the hard mask layer, and then portions of the layers are etched to form a capacitor region over the oxide layer and a contact opening exposing a portion of the source/drain region. In the subsequent step, a conducting layer is formed over the oxide layer, the hard mask layer, the sidewalls of the contact opening and the exposed portion of the source/drain region. Next, a polishing method is used to remove the conducting layer above the oxide layer, and then the oxide layer is removed to form a lower electrode.

Abstract: The present invention relates to a method of manufacturing MOS components having lightly doped drains wherein the implanting type ion used is different than that used in the formation of the source/drain regions. The present invention also includes the use of a tilt implantation angle accompanied by substrate rotation during the implantation process to form lightly doped drain structures on two sides of the source/drain regions. The mask is the same for the formation of the source/drain regions as that for the formation of the lightly doped drain regions. The method of manufacturing MOS components having lightly doped drains according to this invention has fewer manufacturing processes for the formation of spacers than the conventional methods. Moreover, the reduction in spacer production results in an increased contact surface area for subsequent contact window formation, thereby lowering contact resistance.

Abstract: A DRAM is formed by providing a transfer FET, providing an elevated structure over and adjacent to the transfer FET and then forming a cavity above one of the source/drain regions of the transfer FET. The cavity is filled with a conductor to define in part a lower electrode of a charge storage capacitor. Portions of the cavity are then removed to expose additional charge storage surfaces for the lower electrode of the charge storage capacitor. The elevated structure includes a thick, planarized insulating layer provided over the transfer FET. A cavity is formed by providing an etching mask over the thick, planarized insulating layer with an opening positioned over the first source/drain. Etching is performed to remove a portion of the second insulating layer.

Abstract: A DRAM capacitor is formed having a crown structure with a reduced number of processing steps. A planarized insulating layer is provided over the DRAM cell's transfer FET and a contact via is opened to one of the source/drain regions of the transfer FET. A layer of polysilicon is deposited to fill the contact via and to extend over the surface of the insulating layer, providing a thick polysilicon layer on the insulating layer. Conventional photolithography is used to define a first etching mask with an element on the thick polysilicon aligned over the contact via. The polysilicon layer is etched partially through using the first etching mask and the photoresist mask is removed. A layer of oxide is deposited over the elevated and recessed surfaces of the polysilicon layer and an etch back process is performed to form a second etching mask consisting of oxide spacer structures along the edges of the elevated portion of the polysilicon layer.

Abstract: A method of improving the planarization of inter-poly dielectric layers. On a semiconductor device on which a poly-silicon layer is formed, by using atmosphere chemical vapor deposition, an undoped inter-poly dielectric layer is formed. A doped inter-poly dielectric layer is formed on the undoped inter-poly dielectric layer. Under a high temperature, reflow and etching back operations are performed for the doped inter-poly dielectric layer. Before a second poly-silicon layer is formed, a rapid thermal process is performed.

Abstract: A method for forming a LOCOS structure comprising the steps of providing a substrate, then forming a mask layer above the substrate. Next, the mask layer is patterned to form an opening having a depth not more than the mask layer. Subsequently, the mask layer is patterned to form an active device region exposing the substrate that lies outside the area, wherein the opening is within the active device region. Hence, a mask layer having a thicker peripheral section and a thinner middle section over the active device region is formed. Finally, a dielectric layer is formed over the expose substrate to serve as a device isolation structure. This invention provides a thin mask layer over the active device area to prevent the occurrence of excessive stresses, and hence improve the quality of subsequently formed gate oxide layer.

Abstract: A method for fabricating capacitors of a DRAM by employing the liquid-phase deposition. Since the working temperature required for performing liquid-phase deposition is low, selective deposition can be performed on the area not covered by photoresist with the presence of the photoresist layer. The foregoing method comprises: filling up the contact hole with photoresist, and keeping up coating photoresist upward and horizontally; selectively depositing oxide on the area, that is not coated with photoresist, by utilizing the liquid-phase deposition process; removing the photoresist for forming an opening which forms the profile of the lower electrode of a capacitor; forming a conductive layer on the inner walls of the opening, and having the contact hole filled as well to form the lower electrode.

Abstract: A method for fabricating a DRAM capacitor comprising the steps of forming silicon nitride spacers twice, not only serving as etching stop layer in a self-aligned contact etching process, but also used as a protective layer for the bit line and gate electrode in an etching operation. In another aspect, using silicon nitride spacers has the advantage of being capable of increasing the width of a contact opening. Hence, a contact opening having a smaller height to width ratio can be produced. Furthermore, the lower electrode of the capacitor in this invention is a pillar-shaped structure, and together with the formation of a hemispherical grained silicon layer over the lower electrode, the surface area of the capacitor can be greatly increased. Moreover, a dielectric layer having a high dielectric constant can be used; hence, a capacitor with sufficient capacitance can be provided although the surface area of the storage capacitor is reduced.

Abstract: A method for fabricating a semiconductor device is provided comprising forming a dual silicon nitride spacer to be an etching step layer during a self-aligned contact etching step. The invention discloses a bottom electrode with a tri-forked structure and a hemispherical grain layer of a capacitor, therefore the capacitor has a larger surface area. So the capacitor made by the invention has a high capacitance even though the planar surface size is reduced continually.

Abstract: A manufacturing method of fabricating a polysilicon conductive wire suitable for an integrated circuit and which can avoid pattern transfer errors caused by reflection of ultraviolet light during photolithographic processing and that results in constriction in width or the bottlenecking effect in part of the conductive wore. A polysilicon layer is formed above a semiconductor substrate having a preformed device. A cap insulting layer is formed above the polysilicon layer. A micro-roughness structure is formed on the surface of the cap insulating layer. A photoresist layer is coated over the micro-roughened surface of the cap insulating layer. A pattern is transferred onto the photoresist layer by selective light exposure followed by the removal of unexposed photoresist. Then the cap insulating layer and the polysilicon layer are etched in sequence in regions not covered by photoresist. The residual photoresist is then removed to leave behind a polysilicon conductive wire.

Abstract: A method for fabricating capacitors of a DRAM by employing liquid-phase deposition. Since the working temperature required for performing liquid-phase deposition is low, the deposition process can be performed in the presence of the photoresist. This method comprises: filling the contact hole and covering the isolation layer with conductive layer; performing an etching process on the conductive layer by using photoresist and low-temperature spacer as mask; again performing an etching process on the conductive layer, to a desired depth by controlling the etching time and using the low-temperature spacer as mask; removing the low-temperature spacer for finally forming the lower electrode of a cylindrical capacitor.

Abstract: SRAMs conventionally formed on N-type substrates are instead formed on P-type substrates which have had the surface layer of the substrate converted to a blanket N-type well region. Preferably, the blanket N-type well region is formed by ion implantation of phosphorus ions to a dosage of between 5.times.10.sup.12 to 2.times.10.sup.13 /cm.sup.2 at an energy of 200-1000 KeV. Use of a P-type substrate having a blanket N-well region formed by ion implantation are less expensive than the N-type substrates conventionally used, and make the SRAM processing techniques compatible with the P-type substrates conventionally used in microprocessors and other logic devices.

Abstract: A local interconnection structure is disclosed. The local interconnection structure is formed on a silicon substrate in which a polysilicon gate and a number of diffusion regions exist. The structure includes a number of metal silicide layers over the substrate, a metal nitride layer over the silicide layers, and a dielectric layer over the nitride layer. The metal nitride layer which electrically connects the diffusion regions and the gate forms the interconnection. The method for fabricating the interconnection structure includes the steps of preparing the silicon substrate, sputtering a metal layer, annealing to form silicide and the nitride layers, depositing the dielectric layer, and patterning the nitride layer and the metal nitride by covering with a mask, etching away portions of both the dielectric layer and metal nitride layer not covered by the mask, and removing the mask after etching.

Abstract: A bonding pad adapted for use with an Aluminum wire that resists stresses that would otherwise peel the pad from the substrate. The pad has a polysilicon layer adhered to an insulating layer on a semiconductor substrate, a overlying refractory metal polycide layer, a second polysilicon layer, a refractory metal layer, and a thick Aluminum alloy bonding pad.

Abstract: A method of manufacture of a semiconductor device comprises forming a silicon dioxide film upon the surface of said device, forming patterns of silicon nitride upon the surface of said silicon dioxide film, ion implanting ions into said substrate adjacent to at least some of said silicon nitride patterns for well regions of a first polarity, forming a mask over said device, and deeply ion implanting with ions of opposite polarity into well regions of opposite polarity.

Abstract: Device isolation is provided for a MOSFET circuit by providing channel stop regions comprising a distribution of dopants localized beneath and adjacent to corresponding field oxide regions. Channel stop regions are not formed under the channel regions of the MOSFETs and are selectively formed under the narrower field oxide regions which are most likely to provide inadequate device isolation. The channel stop regions are formed subsequent to the formation of field oxide regions, beginning by forming polysilicon spacers so that the polysilicon spacers extend over the bird's beak regions of the field oxide regions. Next, a channel stop mask having openings over selected field oxide regions is formed. Trenches are etched near the center of the exposed field oxide regions, leaving approximately 500 .ANG. of oxide on the bottom of the trench. Ions are implanted through the bottom of the trenches to form channel stop regions beneath the field oxide regions.