Abstract: The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of the capacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

Abstract: The present invention provides a method of fabricating a MOS transistor in an embedded memory. A first dielectric layer, an undoped polysilicon layer, and a second dielectric layer are formed on the periphery circuits area. Next, the undoped polysilicon layer in the memory array area is doped, followed by removal of the second dielectric layer in the memory array area. Then, a silicide layer and a protective layer are formed and portions of the memory array area are etched to form gates. LDDs in each MOS transistor in the memory array area are formed. Next, LDDs in each MOS transistor in the periphery circuits area are formed. A portion of the silicon nitride layer and the silicon oxide layer in the periphery circuits area form a spacer on either side of each gate in the periphery circuits area. Finally, a source and drain (S/D) are formed in the periphery circuits area.

Abstract: A method of fabricating an embedded dynamic random access memory. After a gate and a source/drain region are formed on a semiconductor substrate, an etch stop layer and a dielectric layer are sequentially formed. The dielectric layer is etched back and patterned, and only the dielectric layer over the source/drain region in the memory circuit region remain. The exposed etch stop layer is removed to expose the salicide layer on the gate and the source/drain region in the logic circuit region.

Abstract: A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed.

Abstract: A method of field implantation. Using a photo-resist layer as a mask, a substrate is implanted with ions to forming a selectively distributed ion field.

Abstract: A method of enhancing chemical mechanical polishing uniformity is provided. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of the active area regions in the chip is computed according circuit designs by a program analysis. One of the active area regions with the highest integration is used as a basis, dummy mesas are formed in the other active area regions to adjust the integration of the chip.

Abstract: A self-aligned process for forming a silicide layer over word lines in DRAM and a silicide layer over transistors in a logic device region. A substrate that includes a memory cell region and a logic circuit region is provided. A first transistor and a second transistor are formed over the substrate. The first transistor is formed in the logic circuit region and includes a first gate conductive layer and a first source/drain region. The second transistor is formed in the memory cell region and includes a second gate conductive layer and a second source/drain region. A blocking layer is formed over both the first transistor and the second transistor. A portion of the blocking layer is removed to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer. The remaining blocking layer still covers the second source/drain region. A metal silicide layer is formed over the first gate conductive layer, the first source/drain region and the second gate conductive layer.

Abstract: An ion implantation method useful for fabricating shallow trench isolation structureimplants phosphorus ions instead of arsenic ions into a substrate when the source/drain regions of an NMOS device are doped. Alternatively, low energy ions are used in the ion implantation for forming the source/drain regions of an NMOS device. Consequently lattice dislocations of the crystal structure within a substrate is reduced and unwanted device leakage current is eliminated.

Abstract: A method of manufacturing an embedded memory. A substrate has a memory cell region and a logic circuit region. A plurality of first gate structures and a plurality of second gate structures are respectively formed on the substrate in the memory cell region and the logic circuit region. Every space between the first gate structures is smaller than those between the second gate structures. A first spacer is formed over a sidewall of each first gate structure and over a sidewall of each second gate structure. Several lightly doped drain regions are formed in the substrate exposed by the first spacers and the second gate structures in the logic circuit region. A second spacer is formed on each first spacer in the logic circuit region and a silicide block is simultaneously formed to fill space between the first gate structures in the memory cell region. A source/drain region is formed in the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region.

Abstract: A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed.

Abstract: A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate under the patterned region and the trench is filled with insulator to form an insulation plug, which is a shallow trench isolation. A dielectric layer is formed on the whole substrate surface to cover the device region and the insulation plug.

Abstract: A method of forming contacts is provided. A thin polysilicon layer with a thickness of about 200-400 Å is deposited after forming a contact opening in a substrate. Then, the polysilicon layer is heavily doped using ion implantation to increase the number of mobile carriers in the polysilicon and to destroy the thin oxide layer formed naturally on the substrate, which destruction enhances the contact between the substrate and the polysilicon. A thick polysilicon layer is deposited on the thin polysilicon to form a bit line contact and a node contact.

Abstract: An electrode for a DRAM charge storage capacitor is provided with a textured surface using a wet etching process that has far greater process latitude and a lower cost than conventional processes for forming hemispherical grained silicon. A base capacitor electrode is provided for a DRAM cell preferably having a conventional polysilicon surface on which the textured surface will be formed. A layer of polycrystalline material having a composition different from the polysilicon surface is provided over the polysilicon surface. The layer of polycrystalline material is subjected to a wet etching process which preferentially etches along the grain boundaries of the layer of polycrystalline material. This wet etching process removes portions of the layer of polycrystalline material from over the polysilicon surface. The remaining portions of the layer of polycrystalline material are then used as a mask for etching the surface of the polysilicon, introducing a texture to the surface of the polysilicon layer.

Abstract: A method of fabricating a capacitor of a dynamic random access memory is provided. A substrate is first provided, wherein a first dielectric layer is formed on the substrate, and a via is formed through the first dielectric layer to expose one of source/drain regions. A conductive material is formed on the first dielectric layer so that the conductive material is filled in the via to contact with the one of the source/drain regions. The conductive material is patterned to form a first conductive layer. A hemispherical polysilicon grain layer is formed at least on the first conductive layer. The hemispherical polysilicon grain layer is etched back so that the first conductive layer and the hemispherical polysilicon grain layer together form a lower electrode. A second dielectric layer is formed on the lower electrode. A second conductive layer is formed on the second dielectric layer to be an upper electrode.

Abstract: A method for fabricating a cylinder capacitor of a DRAM cell that starts with forming a first oxide layer and then a doped first polysilicon layer on a substrate, patterning the first polysilicon layer to form a first opening that exposes the first oxide layer, forming a polysilicon spacer at the laterals of the first opening. Then, a portion of the first oxide layer is removed to expose the substrate by using the polysilicon spacer and the first polysilicon layer as a mask. A doped second polysilicon layer is formed on the first polysilicon layer and in the first opening. A portion of the second polysilicon layer is removed to form a second opening. A oxide spacer is formed on the laterals of the second opening, and is used as mask to remove a portion of the second polysilicon layer for forming a lower electrode. A dielectric layer and then a third polysilicon layer are formed on the lower electrode after the silicon oxide spacer is removed, wherein the third polysilicon is an upper electrode.

Abstract: A method of making contact openings for memory cell units of DRAM IC devices is disclosed. The contact opening is used to connect the cell transistor source/drain terminal to the storage capacitor electrode located substantially above. The method includes the step of first patterning the initial opening in a shielding layer for the contact opening. The diameter of the initial opening is then reduced by the formation of sidewall spacers in initial opening. The initial opening in the shielding layer is then used to implement the etching for the formation of the contact opening. Due to reduced size of the contact opening, short-circuiting situations arising between the via formed in the contact opening and the bit lines next to the via as a result of misalignment in the process of fabrication can be reduced, thereby improving the device fabrication yield rates.

Abstract: A planarization method for self-aligned contact process which is suitable for use in DRAM processing. Prior to the formation of the bottom terminal layer of the capacitor, the substrate surface is first planarized, thus avoiding stringer effects and related bridging problems arising from an undulating surface profile, during subsequent etching of the defined pattern. Also according to the method of this invention, by covering the silicon substrate that has MOS transistors laid on top with first a deposition of an oxide layer, then an etch discriminatory layer, and finally a planarization layer, a substrate with a smooth, plane surface is obtained.

Abstract: A method of a method of fabricating a contact. A substrate having a plurality of gates and a plurality of lightly doped source/drain regions is provided. A dielectric layer is formed and patterned to form a self-align contact window to expose a first lightly doped source/drain region of said lightly doped source/drain regions, and to form a first spacer on a side wall of a first gate of said gates simultaneously. An ion implantation is performed by using the first spacer as a mask, so that a first heavily doped source/drain region is formed in the first lightly doped source/drain region. A doped poly-silicon layer is formed over the substrate, and a metal silicide layer is formed on the doped poly-silicon layer. The doped poly-silicon and the metal silicide layer are patterned to form a self-align contact.

Abstract: A method for manufacturing a DRAM capacitor is provided to form a lower electrode with a cylindrical profile by using a first stage and a second stage. The stages provide different etching rates in various situations. The invention uses the stages to allow the part of the second polysilicon layer between the capacitors to be completely etched and prevent the other part of the second polysilicon layer serving as a lower electrode from over-etching. The invention provides an easier process of forming a cylindrical capacitor with a larger surface.

Abstract: The DRAM cell is formed by covering the cell's transfer FET with a conformal insulating layer. A self aligned contact etch removes a portion of the conformal insulating layer from above a first source/drain region of the FET and then a first polysilicon layer is deposited over the device. Etching defines a polysilicon pad from the first polysilicon layer with edges of the polysilicon pad disposed over the gate electrode and an adjacent wiring line. A thick, planarized second insulating layer is provided over the device, filling the volume defined by the locally cupped surface of the polysilicon pad. Etching is performed to remove a portion of the planarized insulating layer using the pad polysilicon layer as an etch stop for the process. A second, thick polysilicon layer is next provided to fill the cavity and the layer is patterned to laterally define the lower capacitor electrode.