Abstract: A process for manufacturing bonding pad adapted for use with an aluminum wire that resists stresses that would otherwise peel the pad from the substrate. The pad has a polysilicon layer adhered to an insulating layer on a semiconductor substrate, a overlying refractory metal polycide layer, a second polysilicon layer, a refractory metal layer, and a thick aluminum alloy bonding pad.

Abstract: A method of forming WSi.sub.x sidewall spacers as an etching stop in the fabrication process of a buried contact. After a gate dielectric layer and a first conducting layer are formed over a substrate, an opening is formed by etching through the gate dielectric layer and first conducting layer. WSi.sub.x sidewall spacers are thereafter formed on the sidewalls of the opening. Then, a second conducting layer is deposited onto the overall surface as well as being connected to the substrate via the opening. When the second and first conducting layers are patterned and etched to form a gate electrode and an interconnect layer, the WSi.sub.x acts as the etching stop to prevent the formation of ditches in the substrate.

Abstract: A method of planarizing an electrical contact region in a silicon substrate uses spin-on-glass or polysilicon as plug material (42) to fill a contact hole (34). A device or doped region (31) is formed at the surface of the substrate (30) and an insulating layer (33) is formed over the substrate so that the entire doped region is covered by the insulating layer. The contact hole is then formed through the insulating layer to expose a portion of the doped region. To increase the conductivity of the doped region through the contact hole, a filler layer of either spin-on-glass or polysilicon, thick enough to substantially fill the contact hole, is formed over the insulating layer. The filler layer is then etched away from the portions around the contact hole by a conventional dry or wet oxide etching process.

Abstract: A process for manufacturing an LDD type of FET, based on the salicide process, is described. Said process does not lead to short circuits between the drain region and and the main body of the FET through the buried contact. The process is based on the use of Liquid Phase Deposition (LPD) as the method for growing the oxide layer from which the spacers are formed. Since oxide layers formed through LPD will deposit preferentially on silicon and silicon oxide surfaces relative to photoresist surfaces, the areas in which the LPD layer forms are readily controlled. This feature allows the buried contact layer to be replaced by an extended drain region which can be connected to other parts of the integrated circuit (by the salicide process) without the danger of shorting paths being formed therein.

Abstract: An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial leveling layer, such as spin-on-glass (SOG) or a anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The leveling layer is then etched back non-selectively by plasma etching to planarize the portion of the field oxide extending above the substrate surface. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.

Abstract: A method for forming an interconnect structure within a semiconductor device. An isolation region which defines an active region is formed upon a semiconductor substrate. A gate electrode is formed upon the active region and an interconnect is formed partially upon the active region and partially upon the isolation region. A low dose ion implant is then provided into the active region not covered by the gate or the interconnect. A pair of insulator spacers are then formed at opposite edges of the gate. A source/drain electrode is then formed within the active region between the gate electrode and the interconnect, and a second source/drain electrode is formed within the active region between the isolation region and the gate. Finally, a metal silicide layer is formed bridging adjoining surfaces of the interconnect and the first source/drain electrode. In a second embodiment, the source/drain electrodes are formed after the metal silicide layer.

Abstract: An SRAM cell includes a semiconductor substrate doped with a dopant of a first type, a highly doped region in the substrate implanted with a dopant of opposite type, a gate oxide layer on the substrate, a first conductive layer formed upon the gate oxide layer, a dielectric layer deposited over the first conductive layer, an opening in the gate oxide layer, the first conductive layer, and the dielectric layer, and a second conductive layer deposited upon the dielectric layer.

Abstract: A method of fabricating an asymmetric lightly doped drain transistor device. The device's drain region is shielded with a barrier layer when ion implantation is applied to a implant a highly doped source region. A large angle implantation then follows to form a lightly doped pocket region adjacent to the highly doped source region. The implantation forming the pocket region increases the doping concentration along the device's source side which increases the device's threshold voltage diminishing short channel effects.

Abstract: A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V.sub.t ' ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V.sub.t1 ions over the entire device.

Abstract: A structure and method is provided for forming a contact plug in a contact hole in a dielectric layer on a semiconductor substrate. A polysilicon spacer is formed on the sidewalls and bottom of the contact hole. A metal, such as titanium, is deposited on the sidewalls and bottom of the hole and on the dielectric layer. The substrate is heated to form a metal silicide layer, such as TiSi.sub.x, and a metal nitride layer, such as TiN, on the side-walls and bottom of the contact hole. Any remaining metal layer and metal nitride layer formed in the heating process is removed. This leaves the titanium silicide layer on the contact hole walls. Tungsten is deposited to fill the contact hole where the metal silicide promotes the nucleation of the tungsten. In a preferred embodiment, to further promote nucleation of the tungsten, a second metal nitride layer is formed on the surface; of the metal silicide layer just prior to tungsten deposition.

Abstract: A structure and method are provided for forming a plug contact and a metal line pattern in a semiconductor device. A contact hole is etched through a first dielectric layer. A second dielectric layer is formed overlying the first layer having first opening that defines a first metal layer and plug contact. A nucleation layer, such as Ti/TiN or Ti/TiW, is formed on the exposed surfaces of the contact hole and first opening. A planarizing layer is formed which fills the contact hole, and at least partially fills the first openings thereby masking portions of the nucleation layer. Unmasked portions of the nucleation layer are removed and then the planarizing layer is removed. A metal is selectively deposited on the remaining nucleation layer portions to fill the contact hole and substantially filling the first opening. The metal in the first opening forms a plug contact to the bottom surface and a metal line pattern. This process has the advantages of forming two metal levels--i.e.

Abstract: An SRAM cell and a process for forming an SRAM cell comprises: forming a gate oxide layer on a semiconductor substrate, forming a gate on the gate oxide layer, forming a first ion implantation into the substrate in areas adjacent to the gate, performing a second ion implantation in an area immediately adjacent to the gate, depositing a dielectric layer over the gates, etching the dielectric layer to form a spacer structure therefrom, with the remainder of the dielectric layer being removed by the etching, and a third ion implantation in the substrate in all regions adjacent to the gates and the spacer forming more highly doped regions adjacent to the gate and the spacer.

Abstract: Improved N-channel and P-channel field effect transistor device structure having self-aligned polysilicon pads contacts and a process for making such devices has been achieved. The doped polysilicon pad contact are formed over the source/drain areas of the field effect transistors and are used to form shallow self-aligned diffused contact to the source/drain areas. These polysilicon pads provide a low resistance ohmic contacts that are free from implant damage that would otherwise cause increased junction leakage current and are free of metal spiking at the source/drain area perimeter that would cause metal contact to substrate shorts. The increased area of the polysilicon pads over the source/drain area allows for relaxed design ground rule for the contact openings, making for a more manufacturable process for Ultra Large Scale Integration applications.

Abstract: A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V.sub.t ' ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V.sub.t1 ions over the entire device.

Abstract: A method for making sub-micron MOS (Metal Oxide Semiconductor) devices, which do not suffer from hot carrier effect, and having improved short-channel effect and improved performance, is described. A silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over the P-well and N-well regions is provided. The P-well region is implanted, in a substantially vertical direction, with a first conductivity-imparting dopant. Gate structures are formed over the P-well and N-well regions. A second conductivity-imparting dopant is implanted, at a large angle to the plane of the silicon substrate, that is of opposite conductivity to the first conductivity-imparting dopant, into the P-well and N-well regions, masked by the gate structures. The N-well region is implanted, in a substantially vertical direction, with a third conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. Sidewall spacers are formed on the gate structures.

Abstract: An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial implant layer, such as CVD oxide, oxynitride or an anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The substrate surface is then implanted with As.sup.75 or p.sup.31 ions penetrating the sacrificial implant layer and forming a implant damaged layer on the field oxide. The implant damaged layer which etches faster in a wet etch in removed selectively thereby making a more planar field oxide structure. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.

Abstract: A method of removing impurities from the surface of an integrated circuit and forming a uniform thin native oxide layer on the same surface of an integrated circuit is described. A hydrofluoric acid solution, followed by a rinse and spin dry, is often used to remove gate oxide from within an opening etched in a polysilicon layer. The rinsing leaves water spots. Spin drying leaves impurities where water tracks were. An H.sub.2 O.sub.2 cleaning is performed to remove the water spots. After the cleaning, a uniform thin layer of native oxide is formed on the surface of the silicon substrate. A second layer of polysilicon is deposited over this first thin native oxide layer and doped with an implant dosage chosen so that it will go through the uniform native oxide layer. The substrate is annealed to drive in the buried contact. Processing continues to form polysilicon or silicide gate electrodes. Source and drain regions are formed within the openings to the silicon substrate between the gate electrodes.