Abstract: A method for fabricating a semiconductor device includes the steps of: (a) forming a plurality of conductive patterns on a substrate in a cell region and a peripheral circuit region; (b) forming an insulation layer on an entire surface of the resulting structure from the step. (a); (c) forming a plurality of plugs in the cell region and simultaneously forming a dummy pattern in a region between the cell region and the peripheral circuit region, each plug and the dummy pattern being contacted to the substrate allocated between the conductive patterns by passing through the insulation layer; (d) forming a photoresist pattern masking the resulting structure in the cell region; and (e) removing the insulation layer in the peripheral circuit region by performing a wet etching process with use of the photoresist pattern as an etch mask to thereby expose a surface of the substrate in the peripheral circuit region.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of improving a gap-fill property of a conductive wire. To achieve this effect, the inventive method includes the steps of: forming a plurality of conductive patterns on a substrate in the first region and the second region, wherein each of the conductive patterns includes sequentially stacked layers of a conductive layer and a hard mask; removing the hard mask in the second region to expose the conductive layer; forming a diffusion barrier layer on the exposed conductive layer; depositing an insulation layer on the entire resulting substrate structure in the first region and the second region; selectively etching the insulation layer in the second region to form an opening exposing the diffusion barrier layer; and forming a conductive wire electrically connected to the diffusion barrier layer through the opening.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing a bit line pattern from being attacked during a storage node contact hole formation. The method includes the steps of: forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group of the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of decreasing a parasitic capacitance to thereby increase a cell capacitance. To achieve this effect, the deposited third inter-layer insulation layer is planarized and is subjected to a wet etching process to make its height lower than that of the bit line. Afterwards, the nitride-based etch stop layer is formed on the etched third inter-layer insulation layer, and then, the contact hole for forming the storage node contact plug is formed in between the bit lines through the SAC process so that the etch stop layer does not remain at sidewalls of the bit line. From this structure, it is possible to decrease the parasitic capacitance, and this decrease further provides an effect of increasing the cell capacitance.

Abstract: A method for fabricating a conducting layer pattern using a hard mask of which a upper surface is flattened by the use of ArF exposure light source.

Abstract: The method forming a contact pad of a semiconductor device, including forming a plurality of conductive layer patterns displaced on a silicon substrate with adjoining to each other; forming an insulating layer on a top of the conductive layer patterns; depositing a material layer serving as a hard mask on the insulating layer; forming a photoresist pattern between the conductive layer patterns on the hard mask material layer to form a contact hole; defining an area for forming a contact by forming by etching the hard mask material layer with utilizing the photoresist pattern as an etching mask; removing the photoresist pattern; exposing the silicon substrate by etching the insulating layer with utilizing the hard mask as an etching mask to thereby form an open portion; forming a polymer layer on the open portion; exposing the silicon substrate by removing the hard mask and the polymer layer by implementing an etch back process; and forming a contacted pad on the exposed silicon substrate.

Abstract: A data latch circuit and method for improving operating speed therein may provide a reduction in delay time. The data latch circuit includes a sense amplifying unit outputting a first signal in response to input data, a first inverted signal in response to a clock signal, a second signal in response to given cascode data, and a second inverted signal in response to the clock signal. A clock latch unit may generate a gated clock signal to enable output of the given cascade data to the sense amplifying unit, in response to an enabling signal and the clock signal. A MUX unit outputs the first signal as output data and the first inverted signal as feedback data, or outputs the second signal as output data and second inverted signal as feedback data, based on the logic level of the enabling signal.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.

Abstract: The present invention provides a method for forming a contact plug of a semiconductor device capable of preventing an attack to conductive patterns. The method includes the steps of: forming a plurality of conductive patterns on a substrate; forming an insulating layer on top of an entire structure including the plurality of the conductive pattern; forming a contact hole by selectively etching the insulating layer; forming a conductive layer for a contact plug on the entire structure including the contact hole; forming a metal sacrificial layer on the entire structure including the conductive layer; exposing the conductive layer by performing an etchback process to the metal sacrificial layer, wherein the metal sacrificial layer is left on a lower topology area induced by the conductive patterns; and forming plugs, each being isolated by polishing the remained metal sacrificial layer, the conductive layer and the insulating layer through the use of slurry.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of preventing a pattern at an edge area of a wafer from being lifted and acting as a particle source. The present invention includes the steps of: preparing a wafer having a first area and a second area, wherein the first area has lower topology than the second area; forming a target layer on the wafer; and patterning the target layer through a photolithography process so to form a number of first patterns in a line shape at the second area and to form a number of second patterns in a closed loop shape at the first area.

Abstract: A method for manufacturing a semiconductor memory device includes the steps of forming a mask layer on a target layer to be etched, coating a photoresist on the mask layer, exposing the photoresist by using a light resource whose wavelength is of about 157 nm to 193 nm, forming a photoresist pattern by developing the photoresist, forming a mask pattern by selectively etching the mask layer with an etching gas except of fluorine-based gases by using the photoresist pattern as an etching mask; and selectively etching the target layer by using the mask pattern as an etching mask.

Abstract: Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.

Abstract: The present invention provides a method for reducing loading capacitance.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first plugs contacted to a substrate by passing through a first inter-layer insulation layer; forming a second inter-layer insulation layer on the first plugs; forming a conductive pattern contacted to a group of the first plugs by etching selectively the second inter-layer insulation layer; and forming a contact hole exposing a surface of the first plug that is not contacted to the conductive pattern by etching selectively the second insulation layer with use of a dry-type and wet-type etch process, wherein an attack barrier layer is formed on between the first inter-layer insulation layer and the second inter-layer insulation layer to thereby prevent an incidence of attack to the first interlayer insulation layer contacted to the first plug during the wet-type etch process for forming the contact hole.

Abstract: The present invention provides a method for forming a contact plug of a semiconductor device capable of preventing an attack to conductive patterns. The method includes the steps of: forming a plurality of conductive patterns on a substrate; forming an insulating layer on top of an entire structure including the plurality of the conductive pattern; forming a contact hole by selectively etching the insulating layer; forming a conductive layer for a contact plug on the entire structure including the contact hole; forming a metal sacrificial layer on the entire structure including the conductive layer; exposing the conductive layer by performing an etchback process to the metal sacrificial layer, wherein the metal sacrificial layer is left on a lower topology area induced by the conductive patterns; and forming plugs, each being isolated by polishing the remained metal sacrificial layer, the conductive layer and the insulating layer through the use of slurry.

Abstract: The present invention provides a method for fabricating a semiconductor device with use of an ArF light source capable of minimizing deformations of a photoresist pattern for ArF during an etching process. Also, when forming the pattern, C5F8 gas is used at a main etching step to compensate etch tolerance of the photoresist for ArF. By controlling process recipe properly, it is possible to minimize pattern deformations as simultaneously as to form a micronized pattern. To compensate the etch tolerance of the photoresist for ArF weaker than that of a photoresist for KrF, the main etching step is divided into three sub-steps, thereby providing a method for minimizing the pattern deformations when duplicating the pattern.

Abstract: Fabricating thin film transistors. A gate electrode is formed on a substrate. A gate oxide film is then formed on the gate electrode. A polysilicon layer is deposited on the gate oxide film. An impurity ion is implanted into the polysilicon layer to control a threshold voltage of the polysilicon layer. A mask is formed on the polysilicon layer above the gate electrode, having the same width as the gate electrode. A second impurity ion is implanted into the exposed portion of the polysilicon layer using the mask, to form a lightly doped offset region on a drain region. The mask is removed. A second mask is formed on the polysilicon layer so as to cover a portion of the gate electrode and the light doped offset region. A Third impurity ion is implanted into the polysilicon layer using the second mask to form source/drain regions. The mask is removed.

Abstract: The present invention relates to a method for fabricating a semiconductor device capable of improving an overlap margin that occurs when forming a conductive pattern, such as a bit line or a bit line contact. In order to achieve this effect, the method for fabricating a semiconductor device includes the steps of: forming a plug passing through an insulation layer to be contacted with a substrate board; forming a planarization insulation layer on an entire surface including the plug so as to cover defects appeared at a surface of the plug; forming a protective insulation layer on the planarization insulation layer for preventing losses of the planarization insulation layer resulted from a subsequent cleaning process; performing a process with an etchant; and forming a conductive layer contacted to the plug by passing through the protective insulation layer and the planarization insulation layer.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of minimizing losses of a gate electrode and a hard mask during a self align contact (SAC) formation process. For this effect, the present invention includes the steps of: forming a plurality of conductive patterns on a substrate; forming hard masks on the conductive patterns; forming an organic based dielectric layer on the substrate including the conductive patterns and the hard mask; forming an oxide based insulation layer on the organic based dielectric layer; etching selectively the insulation layer so as to expose the organic based dielectric layer allocated between the conductive patterns; and etching selectively the exposed organic based dielectric layer to form a contact hole that exposes the surfaces of the substrate between the conductive patterns with an O2 gas as a main etching gas.

Abstract: The present invention to provide a method for fabricating a semiconductor device capable of obtaining a proper process margin resulted from simultaneous formations of via holes in a multi-layered structure having depth differences without an additional process. To achieve this effect, the present invention includes the steps of: forming a first conductive layer; forming a first etching protection layer on the first conductive layer; forming a first insulating layer; forming a second conductive layer on the first insulating layer; forming a second etching protection layer on the second conductive layer, wherein etching protection efficiency of the second protection layer is higher than the first etching protection layer; forming a second insulating layer; and forming a first and a second via hole respectively exposing the first and the second conductive layer by selectively etching the first and the second insulating layer.