Abstract: Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.

Abstract: A method for forming a photoresist pattern with minimally reduced transformations through the use of ArF photolithography, including the steps of: forming an organic anti-reflective coating layer on a an etch-target layer already formed on a substrate; coating a photoresist for ArF on the organic anti-reflective coating layer; exposing the photoresist with ArF laser; forming a first photoresist pattern by developing the photoresist, wherein portions of the organic anti-reflective coating layer are revealed; etching the organic anti-reflective coating layer with the first photoresist pattern as an etch mask and forming a second photoresist pattern by attaching polymer to the first photoresist pattern, wherein the polymer is generated during etching the organic anti-reflection coating layer with an etchant including O2 plasma; and etching the etch-target layer by using the second photoresist pattern as an etch mask.

Abstract: A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating layer; forming a photoresist pattern on the sacrificial layer; forming at least one sacrificial hard mask by etching the sacrificial layer with the photoresist pattern as an etching mask; forming the hard mask by etching the insulating layer with the sacrificial hard mask as an etching mask; and forming a predetermined number of patterns by etching the etch-target layer with use of the sacrificial hard mask and the hard mask as etching masks.

Abstract: A fine pattern forming method of a semiconductor device sequentially deposits an etch-target layer to be formed as the fine pattern, an anti-reflective layer and a photoresist film on a prepared semiconductor substrate and forms a photoresist pattern by performing photolithography for the photoresist film with an ArF exposure source. Then, two etching processes are performed to form the fine pattern. In one etching process, there are etched the anti-reflective layer and a portion of a non-pattern area of the etch-target layer at a first substrate temperature with fluorine-based gas and argon gas by using the photoresist pattern as an etching mask. In the other etching process, there is etched a remaining portion of the non-pattern area of the etch-target layer at a second substrate temperature higher than the first substrate temperature with fluorine-based gas and argon gas.

Abstract: The present invention relates to a method of etching using a photoresist etch barrier formed by an exposure with a light source of which wavelength is in the range of 157 nm to 193 nm, such as an argon fluoride(ArF) laser or fluorine laser(F2 laser), the method includes the steps of coating a photoresist layer on a etch target layer; forming photoresist pattern by developing the photoresist layer after exposing the photoresist layer with a light source of which wavelength is in the range of 157 nm to 193 nm; forming a polymer layer and etching a portion of the etch target layer simultaneously with a mixture of fluorine-based gas, an Ar gas and an O2 gas, wherein the fluorine-based gas is CxFy or CaHbFb, and wherein x, y, a, b and c range from 1 to 10, respectively; and etching the etch target layer using the polymer layer and the photoresist pattern as the etch mask.

Abstract: A fine pattern forming method of a semiconductor device sequentially deposits an etch-target layer to be formed as the fine pattern, an anti-reflective layer and a photoresist film on a prepared semiconductor substrate and forms a photoresist pattern by performing photolithography for the photoresist film with an ArF exposure source. Then, two etching processes are performed to form the fine pattern. In one etching process, there are etched the anti-reflective layer and a portion of a non-pattern area of the etch-target layer at a first substrate temperature with fluorine-based gas and argon gas by using the photoresist pattern as an etching mask. In the other etching process, there is etched a remaining portion of the non-pattern area of the etch-target layer at a second substrate temperature higher than the first substrate temperature with fluorine-based gas and argon gas.

Abstract: A method for manufacturing a semiconductor memory device includes the steps of forming a mask layer on a target layer to be etched, coating a photoresist on the mask layer, exposing the photoresist by using a light resource whose wavelength is of about 157 nm to 193 nm, forming a photoresist pattern by developing the photoresist, forming a mask pattern by selectively etching the mask layer with an etching gas except of fluorine-based gases by using the photoresist pattern as an etching mask; and selectively etching the target layer by using the mask pattern as an etching mask.

Abstract: Disclosed is a method for manufacturing multi-level interconnections using a dual damascene process. The method includes: forming a first interconnection line on a semiconductor substrate; forming a first interlayer insulating layer on the first interconnection line; forming a first etching stop layer on the first interlayer insulating layer; forming a via hole exposing the first interconnection line by selectively etching the first etching stop layer and the first interlayer insulating layer; forming etching stop patterns around an inlet of the via hole by selectively etching the first etching stop layer; forming a second interlayer insulating layer on the etching stop pattern and the first interlayer insulating layer; forming a trench by selectively etching the second interlayer insulating layer; and forming a conductive layer in the trench and in the via hole.

Abstract: A method for manufacturing a metal interconnection includes the steps of, preparing an active matrix provided with a substrate, an insulating layer and an opening formed through the insulating layer, forming a diffusion barrier layer on surfaces of the opening and the insulating layer, forming a protection layer on the diffusion barrier layer, forming a first metal layer into the opening and upon the protection layer, forming a second metal layer on the first metal layer, and polishing back the first and the second metal layer to a top surface of the insulating layer, thereby forming a metal interconnection.

Abstract: A semiconductor device formation method for preventing pattern shift caused by reflow of a glass layer in subsequent thermal processes. An insulating layer having thermal stability at a glass layer reflow temperature of 700° C.-1,000° C. is deposited over a semiconductor substrate to cover a resulting structure formed on the semiconductor substrate. Subsequently, a glass layer is deposited on the insulating layer to planarize topologies, and the glass layer is selectively removed to expose parts of the insulating layer with which conducting patterns are to be contacted. Thereafter, a conducting pattern is formed on the exposed parts of the insulating layer. Using the method, it is possible to prevent the shift of the conducting pattern because the conducting patterns are in contact with the insulating layer having thermal stability.

Abstract: A method for manufacturing a semiconductor device is provided which suppresses migration of lower interconnectors formed on a borophosphosilicate glass (BPSG) layer toward upper interconnectors as a result of secondary reflowing of the BPSG layer during subsequent thermal processing, thereby preventing the formation of electrical shorts.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a transistor on a semiconductor substrate; forming a first interlayer insulating film over the entire structure including the transistor; planarizing the first interlayer insulating film; forming a stabilized insulating film consisting of an insulating material having low thermal expansion and shrinkage on the first interlayer insulating film; forming an interconnection line on the stabilized insulating film; forming a second interlayer insulating film on the stabilized insulating film to cover the interconnection line; and forming a metal electrode on the second interlayer insulating film in order to contact the semiconductor substrate. The interconnection line on the interlayer insulating film does not move as a result of the thermal treatment process, and thus does not cause shorts with the metal electrode. As a result, the leakage current is prevented and the electrical properties of the semiconductor is improved.

Abstract: A semiconductor device formation method for preventing pattern shift caused by reflow of a glass layer in subsequent thermal processes. An insulating layer having thermal stability at a glass layer reflow temperature of 700° C.-1,000° C. is deposited over a semiconductor substrate to cover a resulting structure formed on the semiconductor substrate. Subsequently, a glass layer is deposited on the insulating layer to planarize topologies, and the glass layer is selectively removed to expose parts of the insulating layer with which conducting patterns are to be contacted. Thereafter, a conducting pattern is formed on the exposed parts of the insulating layer. Using the method, it is possible to prevent the shift of the conducting pattern because the conducting patterns are in contact with the insulating layer having thermal stability.

Abstract: A method for manufacturing a semiconductor device is provided which suppresses migration of lower interconnectors formed on a borophosphosilicate glass (BPSG) layer toward upper interconnectors as a result of secondary reflowing of the BPSG layer during subsequent thermal processing, thereby preventing the formation of electrical shorts.

Abstract: A method for manufacturing a metal interconnection includes the steps of, preparing an active matrix provided with a substrate, an insulating layer and an opening formed through the insulating layer, forming a diffusion barrier layer on surfaces of the opening and the insulating layer, forming a protection layer on the diffusion barrier layer, forming a first metal layer into the opening and upon the protection layer, forming a second metal layer on the first metal layer, and polishing back the first and the second metal layer to a top surface of the insulating layer, thereby forming a metal interconnection.

Abstract: Disclosed herein is a method for fabricating thin film transistors comprising the steps of: forming a gate electrode on an insulating substrate; forming a gate oxide film on the insulating substrate and gate electrode; depositing a polysilicon layer on the gate oxide film; implanting a first impurity ion into the polysilicon layer to control a threshold voltage of the polysilicon layer; forming a first ion-implanting mask on a portion of the polysilicon layer above the gate electrode, the first ion-implanting mask having approximately the same width as that of the gate electrode; implanting a second impurity ion into the exposed portion of the polysilicon layer using the first ion implanting mask, to form a lightly doped offset region on a region intended for a drain region; removing the first ion-implanting mask; forming a second ion-implanting mask on the polysilicon layer in such a manner that the second ion-implanting mask covers a portion of the gate electrode and the light doped offset region; implantin