Patents by Inventor Tadashi Miyakawa
Tadashi Miyakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230106886Abstract: According to one embodiment, a method for manufacturing a memory system that has memory cells with a variable resistance element and a switching element connected between a first wire and second wire, includes forming the variable resistance elements in the memory system in a low resistance state or a high resistance state, and then bringing each of the variable resistance elements into the low resistance state before performing either of a read operation or a write operation by performing an external initialization process that is different from the read operation and the write operation. In some examples, the variable resistance element can be a magnetoresistance type element and the external initialization process may be exposing the memory cells to an external magnetic field.Type: ApplicationFiled: February 28, 2022Publication date: April 6, 2023Inventors: Tadashi Miyakawa, Katsuhiko Hoya
-
Patent number: 11101319Abstract: A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.Type: GrantFiled: April 2, 2020Date of Patent: August 24, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tadashi Miyakawa, Katsuhiko Hoya, Hiroyuki Takenaka
-
Publication number: 20200303458Abstract: A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.Type: ApplicationFiled: April 2, 2020Publication date: September 24, 2020Inventors: Tadashi MIYAKAWA, Katsuhiko HOYA, Hiroyuki TAKENAKA
-
Patent number: 10783946Abstract: According to an embodiment, a semiconductor memory device includes: memory cell arrays; word lines respectively connected to rows of each of the memory cell arrays; bit lines respectively connected to columns of each of the memory cell arrays; row selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the word lines; and column selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the bit lines. When an identical row address is received, the row selection circuits perform selection operations of word lines so that word line lengths from selected memory cells to the row selection circuits vary.Type: GrantFiled: March 13, 2019Date of Patent: September 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tadashi Miyakawa, Katsuhiko Hoya
-
Publication number: 20200168263Abstract: According to an embodiment, a semiconductor memory device includes: memory cell arrays; word lines respectively connected to rows of each of the memory cell arrays; bit lines respectively connected to columns of each of the memory cell arrays; row selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the word lines; and column selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the bit lines. When an identical row address is received, the row selection circuits perform selection operations of word lines so that word line lengths from selected memory cells to the row selection circuits vary.Type: ApplicationFiled: March 13, 2019Publication date: May 28, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tadashi MIYAKAWA, Katsuhiko HOYA
-
Publication number: 20180277595Abstract: A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.Type: ApplicationFiled: February 28, 2018Publication date: September 27, 2018Inventors: Tadashi MIYAKAWA, Katsuhiko HOYA, Hiroyuki TAKENAKA
-
Patent number: 10056128Abstract: A semiconductor storage device includes a first memory area; a first selection circuit which selectively connects one of first lines to one of first bit lines of the first memory area, the first lines and the first bit lines extending in a first direction; a second memory area; a second selection circuit which selectively connects one of the first lines to one of second bit lines of the second memory area, the second bit lines extending in the first direction; and a third selection circuit which selectively connects one of the first lines to a global bit line and is arranged between the first selection circuit and the second selection circuit, and configured to select the first selection circuit and the second selection circuit. The first memory area, the first selection circuit, the third selection circuit, the second selection circuit, and the second memory area are aligned in this order in the first direction.Type: GrantFiled: October 18, 2017Date of Patent: August 21, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Fumiyoshi Matsuoka, Tadashi Miyakawa
-
Patent number: 10049711Abstract: According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.Type: GrantFiled: September 6, 2016Date of Patent: August 14, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keisuke Nakatsuka, Tadashi Miyakawa, Katsuhiko Hoya, Takeshi Hamamoto, Hiroyuki Takenaka
-
Publication number: 20180040360Abstract: A semiconductor storage device includes a first memory area; a first selection circuit which selectively connects one of first lines to one of first bit lines of the first memory area, the first lines and the first bit lines extending in a first direction; a second memory area; a second selection circuit which selectively connects one of the first lines to one of second bit lines of the second memory area, the second bit lines extending in the first direction; and a third selection circuit which selectively connects one of the first lines to a global bit line and is arranged between the first selection circuit and the second selection circuit, and configured to select the first selection circuit and the second selection circuit. The first memory area, the first selection circuit, the third selection circuit, the second selection circuit, and the second memory area are aligned in this order in the first direction.Type: ApplicationFiled: October 18, 2017Publication date: February 8, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Fumiyoshi MATSUOKA, Tadashi MIYAKAWA
-
Patent number: 9824738Abstract: According to one embodiment, a semiconductor storage device includes a first memory area, a first selection circuit for selecting a bit line of the first memory area, a second memory area, a second selection circuit for selecting a bit line of the second memory area, and a third selection circuit arranged between the first selection circuit and the second selection circuit and configured to select either the first selection circuit or the second selection circuit.Type: GrantFiled: September 14, 2016Date of Patent: November 21, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Fumiyoshi Matsuoka, Tadashi Miyakawa
-
Publication number: 20170263298Abstract: According to one embodiment, a semiconductor storage device includes a first memory area, a first selection circuit for selecting a bit line of the first memory area, a second memory area, a second selection circuit for selecting a bit line of the second memory area, and a third selection circuit arranged between the first selection circuit and the second selection circuit and configured to select either the first selection circuit or the second selection circuit.Type: ApplicationFiled: September 14, 2016Publication date: September 14, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Fumiyoshi MATSUOKA, Tadashi MIYAKAWA
-
Patent number: 9704918Abstract: A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.Type: GrantFiled: February 19, 2016Date of Patent: July 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tadashi Miyakawa, Katsuhiko Hoya, Mariko Iizuka, Takashi Nakazawa, Hiroyuki Takenaka
-
Patent number: 9646667Abstract: According to one embodiment, a semiconductor memory device includes: a first active area provided in a semiconductor substrate; a second active area provided in the semiconductor substrate and intersecting with the first active area; a first select transistor comprising a first drain region provided in the first active area and a source region provided in an intersection region of the first and second active areas; a second select transistor comprising a second drain region provided in the second active area and sharing the source region; a word line coupled to gates of the first and second select transistors; and first and second variable resistance elements coupled to the first and second drain regions, respectively.Type: GrantFiled: March 9, 2016Date of Patent: May 9, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tadashi Miyakawa, Katsuhiko Hoya
-
Publication number: 20170062030Abstract: According to one embodiment, a semiconductor memory device includes: a first active area provided in a semiconductor substrate; a second active area provided in the semiconductor substrate and intersecting with the first active area; a first select transistor comprising a first drain region provided in the first active area and a source region provided in an intersection region of the first and second active areas; a second select transistor comprising a second drain region provided in the second active area and sharing the source region; a word line coupled to gates of the first and second select transistors; and first and second variable resistance elements coupled to the first and second drain regions, respectively.Type: ApplicationFiled: March 9, 2016Publication date: March 2, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tadashi MIYAKAWA, Katsuhiko HOYA
-
Publication number: 20160379701Abstract: According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.Type: ApplicationFiled: September 6, 2016Publication date: December 29, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keisuke NAKATSUKA, Tadashi MIYAKAWA, Katsuhiko HOYA, Takeshi HAMAMOTO, Hiroyuki TAKENAKA
-
Publication number: 20160197120Abstract: A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.Type: ApplicationFiled: February 19, 2016Publication date: July 7, 2016Inventors: Tadashi MIYAKAWA, Katsuhiko HOYA, Mariko IIZUKA, Takashi NAKAZAWA, Hiroyuki TAKENAKA
-
Patent number: 9368199Abstract: A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array.Type: GrantFiled: December 15, 2014Date of Patent: June 14, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tadashi Miyakawa, Katsuhiko Hoya, Mariko Iizuka, Hiroyuki Takenaka
-
Patent number: 9299409Abstract: According to one embodiment, a semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.Type: GrantFiled: March 7, 2014Date of Patent: March 29, 2016Inventors: Tadashi Miyakawa, Katsuhiko Hoya, Mariko Ilzuka, Takashi Nakazawa, Hiroyuki Takenaka
-
Publication number: 20160064075Abstract: A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array.Type: ApplicationFiled: December 15, 2014Publication date: March 3, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tadashi MIYAKAWA, Katsuhiko HOYA, Mariko IIZUKA, Hiroyuki TAKENAKA
-
Publication number: 20160055895Abstract: According to one embodiment, a semiconductor storage device includes a first storage area including a plurality of memory cells each including a resistance change element which stores data; a second storage area including a plurality of memory cells each including a resistance change element which stores data; a sub memory cell array including the first storage area and the second storage area: a memory cell array including a plurality of sub memory cell arrays arranged along a column direction and a row direction; a third storage area which stores redundancy information and to supply the redundancy information to the sub memory cell array; and a control circuit which controls an access operation to the memory cell array.Type: ApplicationFiled: November 2, 2015Publication date: February 25, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tadashi MIYAKAWA, Katsuhiko HOYA