Abstract: This invention relates to methods for substitution of an amino group of a heterocyclic primary amine by a chlorine atom and synthesis of 2-chloro-5-methylthiazole and its derivatives by application thereof.Typically, a heterocyclic primary amine and sodium nitrite are caused to react in the presence of hydrochloric acid, followed by heating the formed diazonium base at 30.degree.-100.degree. C. in the presence of an equimolar or more of hydrochloric acid to substitute the amino group by the chlorine atom. Further, 2-amino-5-methylthiazole and sodium nitrite are caused to react in the presence of hydrochloric acid, followed by heating the formed diazonium base at 30.degree.-100.degree. C. in the presence of an equimolar or over of hydrochloric acid to give 2-chloro-5-methylthiazole. Then, the resultant 2-chloro-5-methylthiazole is caused to react with a chlorinating agent to give 2-chloro-5-chloro-methylthiazole.

Abstract: The total number of bits of irregular blocks is equal to the number of bits of one equal block. The memory cells of the irregular blocks are sequentially designated using an address counter used to designate the memory cells of equal blocks. An erase operation (including pre program and erase operations) starts from "verify". Only when "verify" is NG, the pre program and erase operations are performed. A means capable of fixing a verify result VERIOK at "1" (verify OK) is arranged to always set VERIOK at "1" for a non-select block of the irregular blocks, thereby preventing execution of the pre program and erase operations for the non-select block of the irregular blocks. Accordingly, in the boot block type, the same address counter is shared by the equal and irregular blocks to reduce the circuit scale.

Abstract: A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.

Abstract: A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.

Abstract: A comparator compares data read out by a sensing amplifier with input data, and outputs equality data when both of the data are equal to each other, while the comparator outputs inequality data when both of the data are not equal to each other. When the comparator outputs inequality data for at least one time within a predetermined period decided by a control signal, the latch circuit latches and keeps outputting the inequality data. The latch circuit latches and outputs equality data when the comparator continuously outputs equality data within the period. Within the period decided by the control signal, the determination circuit determines whether or not writing has been completed on the basis of output data of the latch circuit. The re-write signal generator circuit sends a re-write signal to a write circuit when the determination circuit determines that writing is not yet completed.

Abstract: The non-volatile memory device comprises a memory cell array, a block decoder, and a decode signal reading section. The memory cell array has a plurality of cell blocks. Each of the cell blocks is composed of a plurality of memory cells arranged roughly into a matrix pattern. Each memory cell has a floating gate to or from which electrons are injected or extracted to write or erase data. The block decoder receives a block address, and outputs a decode signal to select a cell block corresponding to the block address from the cell blocks. The memory cells of the selected block are erased simultaneously. When a control signal is inputted to the block decoder, the block decoder outputs the decode signal to select all the cell blocks for erasure of the memory cells of all the cell blocks simultaneously, irrespective of the block address. The decode signal reading section outputs the decode signal to the outside.

Abstract: A method for producing high purity chloroaldehyde monomers at a high yield by depolymerization of a chloroaldehyde cyclic trimer represented by the following formula, ##STR1## wherein R is a hydrogen atom, methyl group, or an ethyl group. The depolymerization reaction can be carried out in the presence of activated clay. Said chloroaldehyde cyclic trimer can be stored in a stable manner and chloroaldehyde monomers obtained by the depolymerization can be used as are as a raw material for the synthetic reaction of chloroaldehyde derivatives.

Abstract: A process for producing dichloroacetaldehyde hydrate together with chloral from acetaldehyde or para-aldehyde. The process comprises a step of chlorinating acetaldehyde or para-aldehyde to obtain a chlorinated solution containing dichloroacetaldehyde as a major component, a step of distilling this chlorinated solution to obtain a distillate having a boiling point of 90.degree.-100.degree. C. and containing 50% or more of dichloroacetaldehyde, a step of adding water to this distillate, crystallizing dichloroacetaldehyde hydrate, and separating the crystals, and a step of chlorinating the remaining aldehyde components into chloral. The process enables dichloroacetaldehyde hydrate to be separated at a high purity and the raw materials to be utilized efficiently.

Abstract: A process for manufacturing a trimer of a low aliphatic aldehyde having 2-5 carbon atoms and the chlorinated 2-position is disclosed. The process comprises cyclically trimerizing said aliphatic aldehyde with chlorinated 2-position in the presence of a catalyst selected from the group consisting of metallic tin, metallic zinc, zeolite, and Lewis acids. It ensures easy separation of the catalyst from the target trimer and a high yield of the trimer. In addition, the unreacted raw material can be easily recovered.

Abstract: A process for manufacturing monochloroacetaldehyde trimer and chloral together by effectively utilizing a raw material acetaldehyde or para-aldehyde. The process comprises a step of chlorinating acetaldehyde or para-aldehyde to produce a chlorinated liquid of which the major component is monochloroacetaldehyde, a step comprising adding chloral to said chlorinated liquid and distilling the mixture to obtain a fraction of which the major components are monochloroacetaldehyde and chloral, a step of trimerizing monochloroacetaldehyde by reacting said fraction in the presence of a trimerization catalyst and separating the MCA trimer by filtration, and a step of chlorinating other fractions from said distillation step and the filtrate from said trimerization step to produce chloral. According to this process all raw material aldehydes and components derived from aldehydes which have not been consumed for the production of MCA trimer can be easily converted into chloral which is useful as an industrial chemical.

Abstract: A memory cell array is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another block (non-selected block) to moderate stress between the floating gate and source/drain, thereby preventing write error and erase error. In the program operation, the source and drain of a memory cell in the non-selected block are equalized to moderate an electric field between the control gate and source/drain and not to flow a channel current, thereby preventing write error. In carrying out a negative voltage erase method, prior to setting the source line and word line of a cell in a non-selected block to an erase voltage, the source and word lines are equalized. The equalization operation is released after the erase operation, thereby preventing malfunction of a non-selected cell.

Abstract: Disclosed herein are a method of and an apparatus for electrically processing an image, and a calibration chart used in the apparatus.

Abstract: A novel compound, a 2-chloropropionaldehyde trimer and a process of producing a 2-chloropropionaldehyde trimer by adding concentrated sulfuric acid to an organic solvent containing 2-chloropropionaldehyde and stirring the mixture at a temperature of from -5.degree. C. to 15.degree. C. to carry out the reaction.

Abstract: According to this invention, the original cassette accommdates the color originals having difference sizes The original cassette is mounted on an original board. Plane scanning is carried out without causing flare by use of an image sensor in accordance with a transmissive method or a reflective method. Auxiliary scanning is then effected after executing a linear reading process, thereby obtaining image data of the whole. Printing plates of CMY and black (K) are directly outputted. Processing is performed by executing rough prescanning and fine main scanning when reading the image. The conditional parameters for processing the images are automatically (or manually) set based on the data stored. The images can be outputted at a high efficiency from a relation between the original and the photosensitive material. The image processing system of this invention has a function to indicate a speed preference mode, a photosensitive material consumption preference mode an a quality preference mode.

Abstract: A color original such as a color reversal film and the like which may be different size (for example, the Brownie, 4".times.5", 35 mm) is fitted or stored in the original cassette mounted on the cassette base. The original is read to obtain a whole image data by a transmission type or a reflection type image sensor without catching any flare, and an auxiliary scanning is done sequentially on lines of the original, reading the whole surface thereof, so as to output directly the plates of C,M,Y and black (K). Because of the procedure described above the operation to produce the plates is easily done at a high speed by even an unskilled operator. The operation for scanning the original image comprises the steps of scanning (pre-scanning) the original image in rough, and then scanning (main scanning) it in detail. The original image is displayed in accordance with data of the pre-scanning and the data of the pre-scanning is stored in a memory.

Abstract: Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate.

Abstract: First image information recorded on a first subject copy is read for establishing processing conditions, and processing conditions are established based on the first image information which has been read. At the same time that the processing conditions are established based on the first image information, second image information recorded on a second subject copy is read for establishing processing conditions. The first image information recorded on the first subject copy is read again according to the established processing conditions to obtain output image information to be reproduced. Alternatively, processing conditions are established based on the second image information that has been read, at the same time that the first image information recorded on the first subject copy is read according to the established processing conditions.

Abstract: Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate.

Abstract: An image information reading system comprising a plurality of preset apparatuses each having a first scan mechanism for reading image information carried by an original while scanning the same, and a processing condition setting-up device for setting up scanning conditions of the read image information and image processing conditions used to process the read image information, and at least one main scan apparatus having a second scan mechanism for reading image information recorded on an original while scanning the same, and an image information processing device for processing the image information read by the second scan mechanism on the basis of the scanning conditions and the image processing conditions determined by any one of the preset apparatuses.

Abstract: According to the present invention, the image input apparatus is adapted to sample the image signal read by the linear image sensor by means of the sampling means in order to output image data.